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參數(shù)資料
| 型號： | pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Processor With MMX And Mobile Module(32位帶移動模塊和MMX技術(shù)CPU) |
| 中文描述： | 32位處理器MMX和移動模塊（32位帶移動模塊和MMX公司技術(shù)的CPU） |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 550K |
| 代理商： | PENTIUM PROCESSOR |
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INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
E
2.1.7.
ITP/JTAG (7 SIGNALS)
14
9/19/97 1:03 PM SPEIDEN_.DOC
Table 8 lists the
Intel Mobile Module’s In-target
Probe (ITP)/JTAG signals, which the I/O Module
can use to implement a processor debug port. The
system manufacturer can use debug port signals
on development-level boards, or on production
boards
for
manufacturing
testability.
Refer to the
Intel Mobile Module Design Guide
(Order Number 243339) for further details on
recommendations and requirements for a debug
port.
Termination for the ITP signals must be done on
the I/O Module. The Intel Mobile Module does not
provide series termination for these signals.
Table 8. ITP/JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUIO
JTAG Test Data Out:
Serial output port. TAP instructions and data
are shifted out of the processor from this port.
TDI
I
V_CPUIO
JTAG Test Data In:
Serial input port. TAP instructions and data are
shifted into the processor from this port.
TMS
I
V_CPUIO
JTAG Test Mode Select:
Controls the TAP controller change
sequence.
TCLK
I
V_CPUIO
JTAG Test Clock:
Testability clock for clocking the JTAG boundary
scan sequence.
TRST#
I
V_CPUIO
JTAG Test Reset:
Asynchronously resets the TAP controller in the
processor.
ITP(1:0)
ITP1: PRDY
ITP0: R/S#
O
I
V_CPUIO
Debug Port Signals:
Currently defined for the generation of
Pentium processors. Future uses are not yet defined.
NOTE:
ITP(1:0) are used to define two pins for the debug port. At this time, these signals are defined as follows for
Pentium
processors:
ITP1:
PRDY
ITP0:
R/S#
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