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| 型號： | pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Processor With MMX And Mobile Module(32位帶移動(dòng)模塊和MMX技術(shù)CPU) |
| 中文描述： | 32位處理器MMX和移動(dòng)模塊（32位帶移動(dòng)模塊和MMX公司技術(shù)的CPU） |
| 文件頁數(shù)： | 7/35頁 |
| 文件大?。?/td> | 550K |
| 代理商： | PENTIUM PROCESSOR |
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E
INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
7
9/19/97 1:03 PM SPEIDEN_.DOC
2.1.1.
MEMORY (108 SIGNALS)
Table 2 lists the Intel Mobile Module memory
interface signals. Some signals are defined as
“RESERVED” for future use. Signals marked with
an * are terminated with a 22
series resistor.
Table 2. Memory Signal Descriptions
Name
Type
Voltage
Description
MPD[7:0]
I/O
V_3S
Memory Parity Data:
These signals connect to the DRAM parity.
These pins are not implemented in the 430TX PCIset and are
reserved.
*RAS[5:0]# or
CS[5:0]#
O
V_3S
Row Address Strobe (EDO):
These pins select the DRAM row.
Chip Select (SDRAM):
These pins activate the SDRAMs.
SDRAM
accepts any command when its CS# pin is active low.
*CAS[7:0]# or
DQM[7:0]
O
V_3S
Column Address Strobe (EDO):
These pins select the DRAM
column.
Input/Output Data Mask (SDRAM):
These pins act as synchronized
output enables during a read cycle and as a byte mask during a write
cycle.
*MA[13:0]
O
V_3S
Memory Address (EDO/SDRAM):
This is the row and column
address for DRAM.
These buffers now include programmable size
selection, as controlled by the DRAMEC[MAD] bit.
The 430TX PCIset
implements (and the Intel Mobile Module supports) only MA[13:0].
See Figure 3 for more details.
*MWE[A,B]#
O
V_3S
Memory Write Enable (EDO/SDRAM):
MWE[A,B]# should be used
as the write enable for the memory data bus.
Each copy is intended to
support four rows, for loading purposes.
*SRAS[A,B]#
O
V_3S
SDRAM Row Address Strobe (SDRAM):
When active low, this
signal latches Row Address on the positive edge of the clock. This
signal also allows Row access and pre-charge. Each copy is intended
to support four rows, for loading purposes.
The SRASA signal is used to configure the Mobile Mode of the 430TX
PCIset.
When the RST# signal is active, SRASA is an input.
The Intel
Mobile Module has a pull-down resistor so that SRASA is sampled
low at the rising edge of RST#;
thereby configuring the 430TX PCIset
in Mobile Mode.
*SCAS[A,B]#
O
V_3S
SDRAM Column Address Strobe (SDRAM):
When active low, this
signal latches Column Address on the positive edge of the clock.
This
signal also allows Column access. Each copy is intended to support
four rows, for loading purposes.
*CKE[A,B]#
O
V_3S
SDRAM Clock Enable (SDRAM):
SDRAM
clock enable pin.
When
these signals are de-asserted, SDRAM enters power-down mode.
Each copy is intended to support four rows, for loading purposes.
MD[63:0]
I/O
V_3S
Memory Data:
These signals are connected to the DRAM data bus.
They are not terminated on the Intel Mobile Module and it is
recommended that the I/O Module provide series termination of 33
.
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