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| 型號： | pentium pro processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器) |
| 中文描述： | 奔騰Pro處理器在200MHz（1兆比特二級高速緩存頻率200兆赫茲處理器帶有1MB的L2緩存） |
| 文件頁數(shù)： | 24/39頁 |
| 文件大?。?/td> | 930K |
| 代理商： | PENTIUM PRO PROCESSOR |
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AP-523
E
24
Table 4. Estimating V
TT
Current
Quantity of Signals
Signal Group
Maximum Duty Cycle
Average Current
Data + ECC
72
100
3.24
Address + Parity
35
67
1.06
Arbitration
7
100
0.32
Request
7
67
0.21
Error
5
20
0.05
Response
6
33
0.09
Other
9
100
0.41
Total
141
5.38
The maximum current that a GTL+ buffer will sink is 45
mA. When considering the duty cycle of the signals, the
maximum current that the 141 signals will draw is about
5.38 Amps at 100% utilization of the bus. Notice that the
duty cycles are chosen rather conservatively in Table 4.
The actual current will be limited by the utilization of the
bus and by the value of the termination resistors in the
design. These benefits can be taken into account as well.
5.1.
Tolerance
The tolerance specification is 150 mV.
important to note that this tolerance specification covers
all voltage anomalies including power supply ripple,
power supply tolerance, current transient response, and
noise. Not meeting the specification on the low or high
end will change the rise and fall time specifications.
Failure to meet this specification on the low end will also
result in reduced margins for the GTL+ buffers thus
making it more difficult to meet timing specifications.
It is again
5.2.
Reference Voltage
The GTL+ bus requires a Voltage Reference called V
REF
as well. V
REF
is to be set at 2/3 V
TT
. The current draw on
this signal is very low (at most 15
m
A per device) and can
be created by a simple voltage divider of two resistors.
Bear in mind that the leakage current can vary and may
be significant when building the voltage divider.
6.0.
MEETING THE GTL+ POWER
REQUIREMENTS
Due to the different nature of powering the GTL+ bus
versus powering a processor, meeting the V
TT
requirements may be addressed in a different way.
6.1.
Generating V
TT
Since the GTL+ bus must be terminated on both ends of
the bus, it may be convenient in many designs to
generate V
TT
on each end of the line. Each will only be
required to supply one half of the current necessary to the
GTL+ drivers. If both ends of the bus are fairly near each
other, then one supply could suffice.
When powering the bus from a single regulator, the
techniques of design will closely resemble those of
Section 4 and a full analysis should be run.
When powering each end of the bus separately, the
current will be low enough that a linear regulator can
reasonably be used to generate it. Linear regulators are
faster devices than switching regulators and will
therefore require less output decoupling. Also, due to the
lower current, the ESR and ESL of components will not
be as large an issue as before. A proper analysis as in
described in Section 4 could be considered. The
techniques would remain the same, while the reaction
time of the supply and the current levels will be different.
It is not necessary for these two regulators to track each
other as long as each maintains the specification on V
TT
.
The bus will naturally perform an averaging function on
these two inputs which must also be followed by V
REF
as
discussed in Section 6.3.
6.2.
Distributing V
TT
V
TT
is only needed at the termination resistors and for
generation of V
REF
. If the distance to the termination
resistors is small, distributing V
TT
with a wide trace
should be sufficient. The trace to the V
REF
generation
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