參數(shù)資料
型號(hào)： pentium pro processor
廠商： Intel Corp.
英文描述： Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器)
中文描述： 奔騰Pro處理器在200MHz（1兆比特二級(jí)高速緩存頻率200兆赫茲處理器帶有1MB的L2緩存）
文件頁(yè)數(shù)： 12/39頁(yè)
文件大小： 930K
代理商： PENTIUM PRO PROCESSOR
AP-523
E
12
inputs use a 5V input for their ESD protection. This
eliminates any issue with turning on its ESD diodes.
If there are 5V PCI cards in the system, it would also be
prudent to supply a weak pull-down on the PCI_RST#
line for the event that 5V is on while 3.3V is off.
3.3.5.
CLOCK INPUT
The clock input frequency must never exceed the
intended final value while the PWRGOOD signal to the
processor is active. (See terminology in Section 1.1)
PWRGOOD should be inactive anytime that V
CC
P or
3.3V are invalid. This can be accomplished by logically
OR-ing the PWRGOOD signals from both supplies, and
connecting this output to the chipset and the Pentium Pro
processor Power-Good inputs (pin names may vary) for
reset generation. (In this case, PWRGOOD is a signal
from each supply that signals when its voltage level is
stable and within tolerance.)
3.3.6.
CLOCK RATIO INPUTS
The pins A20M#, IGNNE#, LINT1, and LINT0 are
shared with the function for programming the PLL core
clock multiplier ratio. These pins control the setting of
the clock multiplier ratio during RESET# and until two
clocks beyond the end of the RESET# pulse. At all other
times their functionality is defined as the compatibility
signals that the pins are named after. These signals have
been made 3.3V tolerant so that they may be driven by
existing logic devices. This is important for both
functions of the pins.
Figure 10 shows the timing relationship required for the
clock ratio signals with respect to RESET# and BCLK.
Table 1 shows the timing parameters. Note that the
minimum setup time for these signals is 1 ms. This table
also shows the timing relationship of the compatibility
signals. A signal called CRESET# (CMOS Reset) is
shown, with the timing needed for controlling the
multiplexing function required to share the pins. This
may be provided by the chipset.
CRESET#
Final
Ratio
Compatibility
BCLK
RESET#
Ratio pins#
t1
t2
t3
t4
≤
Final
Ratio
t5
Figure 10. Timing Diagram of Compatibility Pins
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