- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367809 > PCA9665 (NXP Semiconductors N.V.) Fm+ parallel bus to I2C-bus controller PDF資料下載
參數(shù)資料
| 型號： | PCA9665 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Fm+ parallel bus to I2C-bus controller |
| 中文描述： | 調(diào)頻并行總線I2C總線控制器 |
| 文件頁數(shù)： | 49/91頁 |
| 文件大小： | 372K |
| 代理商： | PCA9665 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁
PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
49 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
3. Program I2CCON register to initiate the Master Receiver Buffered sequence. In
Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and
the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA
register contains the status of the transmission. MODE bit must be set to ‘1’ each time
a write to the I2CCON register is performed.
4. After reading the I2CSTA status register, the I2CCON is programmed with STA = 0.
That clears the previous Interrupt. If a START command has been previously sent, the
I
2
C-bus address + R/W = 1 byte that has been loaded into the buffer is sent to the
I
2
C-bus, the PCA9665 then becomes a master receiver device and starts receiving
data from the addressed slave device.
Remark:
The PCA9665 is already a master receiver device if a buffered sequence
has been previously executed.
5. When the sequence has been executed, an Interrupt is asserted and the SI bit is set
in the I2CCON register. The I2CSTA register contains the status of the transmission
and the I2CCOUNT register contains the number of bytes that have been received.
I2CDAT buffer contains all the data that has been received and can be read by the
microcontroller.
6. More sequences (program the I2CCOUNT register, write to the I2CCON register, read
the I2CSTA register when sequence has been executed, read the I2CDAT buffer) can
be performed as long as a STOP or a Repeated START command has not been sent.
To be able to end the reception, the last buffered sequence must be performed with
LB = 1. Master Receiver Buffered mode ends when the I2CCOUNT register is
programmed with STO = 1.
8.5.3
Buffered Slave Transmitter mode
1. An interrupt is asserted and the SI bit is set in the I2CCON register when the
PCA9665’s own slave address has been detected on the I
2
C-bus (AA = 1, own slave
address defined in the I2CADR register). In Slave Transmitter mode, R/W = 1.
2. Program the I2CCOUNT register with the number of bytes that need to be sent to the
I
2
C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver Buffered
mode only.
3. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in
the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If
more than 68 bytes are written to the buffer, the data at address 00h will be
overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to
BC[6:0] in the I2CCOUNT register. The number of data bytes sent is equal to BC[6:0],
therefore, if the number of data bytes loaded is greater than BC[6:0], the additional
data will not be sent. If the number of data bytes written to the buffer is less than
BC[6:0], the PCA9665 will still send out BC[6:0] data bytes.
4. The I2CCON is programmed to clear the previous Interrupt. The bytes loaded into the
buffer are sent to the I
2
C-bus. MODE bits must be set to ‘1’ each time a write to the
I2CCON register is performed.
5. When the sequence has been executed (BC[6:0] bytes sent or the master sent a
NACK), an Interrupt is asserted and the SI bit is set in the I2CCON register. The
I2CSTA register contains the status of the transmission and the I2CCOUNT register
contains the number of bytes that have been sent to the I
2
C-bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCA9665N | Fm+ parallel bus to I2C-bus controller |
| PCA9671 | Remote 16-bit I/O expander for Fm+ I2C-bus with reset |
| PCA9671DB | Remote 16-bit I/O expander for Fm+ I2C-bus with reset |
| PCA9671DK | Remote 16-bit I/O expander for Fm+ I2C-bus with reset |
| PCA9673 | Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCA9665APW,118 | 功能描述:I2C 接口集成電路 Fm+ parallel bus I2C bus controller RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665BS,118 | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665BS-T | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665D | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
| PCA9665D,112 | 功能描述:I2C 接口集成電路 FM+ I2C BUS CONTRLLR RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。