參數(shù)資料
型號(hào)： PCA9665
廠商： NXP Semiconductors N.V.
英文描述： Fm+ parallel bus to I2C-bus controller
中文描述： 調(diào)頻并行總線I2C總線控制器
文件頁(yè)數(shù)： 48/91頁(yè)
文件大?。?/td> 372K
代理商： PCA9665
PCA9665_2
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 7 December 2006
48 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
8.5 Buffered mode examples
8.5.1
Buffered Master Transmitter mode of operation
1. Program the I2CCOUNT register with the number of bytes that need to be sent to the
I
2
C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver mode only
and can be set to 0 or 1.
2. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in
the PCA9665 buffer. There is no protection against writing over a buffer’s boundary. If
more than 68 bytes are written to the buffer, the data at address 00h will be
overwritten. The number of bytes that needs to be loaded in I2CDAT is equal to
BC[6:0] in the I2CCOUNT register. The number of data bytes sent is equal to BC[6:0],
therefore, if the number of data bytes loaded is greater than BC[6:0], the additional
data will not be sent. If the number of data bytes written to the buffer is less than
BC[6:0], the PCA9665 will still send out BC[6:0] data bytes.
3. Program I2CCON register to initiate the Master Transmitter Buffered sequence. In
Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and
the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA
register contains the status of the transmission. MODE bit must be set to ‘1’ each time
a write to the I2CCON register is performed.
4. After reading the I2CSTA status register, the I2CCON is programmed with STA = 0.
That clears the previous Interrupt. If a START command has been previously sent, the
first byte loaded into the buffer and sent to the I
2
C-bus is interpreted as the
I
2
C-bus address + R/W operation. In transmitter mode, R/W = 0 and the following
bytes that are sent to the I
2
C-bus are interpreted as data bytes.
5. When the sequence has been executed, an Interrupt is asserted and the SI bit is set
in the I2CCON register. The I2CSTA register contains the status of the transmission
and the I2CCOUNT register contains the number of bytes that have been sent to the
I
2
C-bus as described in
Table 42
.
6. More sequence (program I2CCOUNT register, load data bytes in I2CDAT buffer, write
the I2CCON register to send the data to the I
2
C-bus, read the I2CSTA register when
the sequence has been executed) can be performed as long as a STOP or Repeated
START command has not been sent. Master Transmitter Buffered mode ends when
the I2CCOUNT register is programmed with STO = 1.
8.5.2
Buffered Master Receiver mode of operation
1. Program the I2CCOUNT register with the number of bytes that need to be read from a
slave device in the I
2
C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used in
Receiver mode to let the PCA9665 know if the last byte received must be
acknowledged or not.
LB = 0: Last received byte is acknowledged and another sequence can be executed.
LB = 1: Last received byte is not acknowledged. The last sequence before sending a
STOP or Repeated START must be executed with LB = 1.
2. Load the I
2
C-bus address + R/W = 1 in I2CDAT buffer.
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