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參數(shù)資料
| 型號： | PC7410 |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7410 RISC Microprocessor Product Specification |
| 中文描述： | 7410的PowerPC RISC微處理器產(chǎn)品規(guī)格 |
| 文件頁數(shù)： | 6/54頁 |
| 文件大小： | 692K |
| 代理商： | PC7410 |
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PC7410
2141D–HIREL–02/04
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Level 2 (L2) Cache Interface
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Internal L2 cache controller and tags; external data SRAMs
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512K, 1M and 2-Mbyte 2-way set associative L2 cache support
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Copyback or write-through data cache (on a page basis or for all L2)
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32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size
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Supports pipelined (register-register) synchronous burst SRAMs and
pipelined (register-register) late-write synchronous burst SRAMs
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Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM
(either all, half or none of L2 SRAM must be configured as direct mapped.
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Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4
supported
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64-bit data bus which also support 32-bits bus mode
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Selectable interface voltages of 1.8V and 2.5V
Memory Management Unit
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128 entry, 2-way set associative instruction TLB
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128 entry, 2-way set associative data TLB
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Hardware reload for TLBs
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Four instruction BATs and four data BATs
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Virtual memory support for up to four petabytes (2
52
) of virtual memory
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Real memory support for up to four gigabytes (2
32
) of physical memory
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Snooped and invalidated for TLBI instructions
Efficient Data Flow
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All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are
128 bits wide
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dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF
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L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
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Up to eight outstanding out-of-order cache misses between dL1 and L2/bus
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Up to seven outstanding out-of-order transactions on the bus
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Load folding to fold new dL1 misses into older outstanding load and store
misses to the same line
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Store miss merging for multiple store misses to the same line. Only
coherency action taken (i.e., address only) for store misses merged to all 32
bytes of a cache line (no data tenure needed).
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Two-entry finished store queue and four-entry completed store queue
between load/store unit and dL1
32K 32-byte line, 8-way set associative data cache (dL1)
Single-cycle cache access
Pseudo least-recently-used (LRU) replacement
Data cache supports AltiVec LRU and transient instructions algorithm
Copy-back or write-through data cache (on a page-per-page basis)
Supports all PowerPC memory coherency modes
Non-blocking instruction and data cache
Separate copy of data cache tags for efficient snooping
No snooping of instruction cache except for ICBI instruction
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相關(guān)代理商/技術(shù)參數(shù) |
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| PC7410M16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PC7410M16 [Updated 12/02. 35 Pages] |
| PC7410MG400LE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG400NE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG450LE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG450NE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
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