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參數(shù)資料
| 型號： | PC7410 |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7410 RISC Microprocessor Product Specification |
| 中文描述： | 7410的PowerPC RISC微處理器產(chǎn)品規(guī)格 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 692K |
| 代理商： | PC7410 |
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PC7410
2141D–HIREL–02/04
7. All other output signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI, DH[0:31],
DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.
8. Output valid time is measured from 2.4V to 0.8V which may be longer than the time required to discharge from Vdd to 0.8V.
9. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low
then precharged high before returning to high-Z as shown in Figure 9. The nominal precharge width for ABB or DBB is 0.5 x
t
SYSCLK
, i.e., less than the minimum t
SYSCLK
period, to ensure that another master asserting ABB, or DBB on the following
clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid
time is tested for precharge.The high-Z behavior is guaranteed by design.
10. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately fol-
lowing AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting
it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle
after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 t
SYSCLK
; i.e., it should be high-Z as shown in Fig-
ure 9 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are tested for the
signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.
11. Guaranteed by design and not tested.
12. Output hold time characteristics can be altered by the use of the L2_TSTCK pin during system reset, similar to L2 output
hold being altered by the use of bits [14-15] in the L2CR register. Information on the operation of the L2_TSTCLK will be
included in future revisions of this specification.
Figure 9.
Input/Output Timing Diagram
t
IVKH
t
IXKH
t
KHOV
t
KHOX
t
KHOE
t
KHOZ
t
KHTSV
t
KHTSV
t
KHTSX
t
KHABPZ
t
KHARV
t
KHARV
t
KHARPZ
t
KHARP
t
KHARX
VM = Midpont Voltage (OV
DD
/2)
SYSCLK
All Inputs
VM
VM
VM
All Outputs
(except TS, ABB,
ARTRY, DBB)
TS,
ABB/AMON[0],
DBB/DMON[0]
All Outputs
(except TS, ABB,
ARTRY, DBB)
ARTRY,
SHD0,
SHD1
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