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參數(shù)資料
| 型號(hào)： | PC7410 |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7410 RISC Microprocessor Product Specification |
| 中文描述： | 7410的PowerPC RISC微處理器產(chǎn)品規(guī)格 |
| 文件頁數(shù)： | 44/54頁 |
| 文件大?。?/td> | 692K |
| 代理商： | PC7410 |
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44
PC7410
2141D–HIREL–02/04
During inactive periods on the bus, the address and transfer attributes may not be
driven by any master and may, therefore, float in the high-impedance state for relatively
long periods of time. Since the PC7410 must continually monitor these signals for
snooping, this float condition may cause excessive power draw by the input receivers on
the PC7410 or by other receivers in the system. These signals can be pulled up through
weak (10 k
) pull-up resistors by the system, address bus driven mode can be enabled
(see the PC7410 RISC Microporcessor Family Users’ Manual for more information on
this mode), or these signals may be otherwise driven by the system during inactive peri-
ods of the bus to avoid this additional power draw. The snooped address and transfer
attribute inputs are: A[0:31], AP[0:3], TT[0:4], CI, WT, and GBL.
In systems where GBL is not connected and other devices may be asserting TS for a
snoopable transaction while not driving GBL to the processor, we recommend that a
strong (1 k
) pull-up resistor be used on GBL. Note that the PC7410 will only snoop
transactions when GBL is asserted.
The data bus input receivers are normally turned off when no read operation is in
progress and, therefore, do not require pull-up resistors on the bus. Other data bus
receivers in the system, however, may require pull-ups, or that those signals be other-
wise driven by the system during inactive periods by the system. The data bus signals
are: DH[0:31], DL[0:31], and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is
disabled through HID0, the input receivers for those pins are disabled, and those pins
do not require pull-up resistors and should be left unconnected by the system. If parity
checking is disabled through HID0, and parity generation is not required by the PC7410
(note that the PC7410 always generates parity), then all parity pins may be left uncon-
nected by the system. The L2 interface does not normally require pull-up resistors.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC7410M16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PC7410M16 [Updated 12/02. 35 Pages] |
| PC7410MG400LE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG400NE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG450LE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG450NE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
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