參數(shù)資料
型號： PC7410
廠商： Atmel Corp.
英文描述： PowerPC 7410 RISC Microprocessor Product Specification
中文描述： 7410的PowerPC RISC微處理器產(chǎn)品規(guī)格
文件頁數(shù)： 20/54頁
文件大?。?/td> 692K
代理商： PC7410
20
PC7410
2141D–HIREL–02/04
8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see V
IL
/V
IH
/V
OL
/V
OH
/CV
IH
/CV
IL
DC limits of 1.8V mode
while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by the UpdateIR TAP state
until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state.
If only TSRT is asserted to the part, and then a SAMPLE instruction is executed, there is no way to control or predict what
the DC voltage limits are. If HRESET is asserted before executing a SAMPLE instruction, the DC voltage limits will be con-
trolled by the BVSEL/L2VSEL settings during HRESET. Anytime HRESET
is not asserted (i.e., just asserting TRST
)
, the
voltage mode is not known until either EXTEST or CLAMP is executed, at which time the voltage level will be at the DC limits
of 1.8V.
Dynamic Characteristics
After fabrication, parts are sorted by maximum processor core frequency as shown in
“Clock AC Specifications” and tested for conformance to the AC specifications for that
frequency. These specifications are for valid processor core frequencies. The processor
core frequency is determined by the bus (SYSCLK) frequency and the settings of the
PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency.
Clock AC Specifications
Table 10 provides the clock AC timing specifications as defined in Figure 8.
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) fre-
quency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in “Clock Selection” on page 39 for valid PLL_CFG[0:3] settings
2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OV
DD
= 3.3V nominal.
3. Rise and fall times for the SYSCLK input measured from 0.2V to 1.2V when OV
DD
= 1.8V or 2.5V nominal.
4. Timing is guaranteed by design and characterization.
5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.
6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
PLL lock after a stable V
DD
and SYSCLK are reached during the power-on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Table 10.
Clock AC Timing Specifications (See Table 4 for Recommended Operating Conditions
)
Symbol
Characteristic
Maximum Processor Core Frequency
Unit
400 MHz
450 MHz
500 MHz
Min
Max
Min
Max
Min
Max
f
CORE
(1)
Processor frequency
350
400
350
450
350
500
MHz
f
VCO
(1)
VCO frequency
700
800
700
900
700
1000
MHz
f
SYSCLK
(1)
SYSCLK frequency
33
133
33
133
33
133
MHz
t
SYSCLK
SYSCLK cycle time
7.5
30
7.5
30
7.5
30
ns
t
KR
&
t
KF
t
KR
&
t
KF
t
KHKL
/t
SYSCLK
(2)
SYSCLK rise and fall time
1.0
1.0
1
ns
(3)
0.5
0.5
0.5
ns
(4)
SYSCLK duty cycle measured at OV
DD
/2
SYSCLK jitter
(5)
40
60
40
60
40
60
%
±150
±150
±150
ps
Internal PLL relock time
(6)
100
100
100
μs
相關PDF資料
PDF描述
PC7410MGHU400L PowerPC 7410 RISC Microprocessor Product Specification
PC7410VGU450N PowerPC 7410 RISC Microprocessor Product Specification
PC7410VGU500L PowerPC 7410 RISC Microprocessor Product Specification
PC7410VGU500N PowerPC 7410 RISC Microprocessor Product Specification
PC7410MGU450L PowerPC 7410 RISC Microprocessor Product Specification
相關代理商/技術參數(shù)
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PC7410M16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PC7410M16 [Updated 12/02. 35 Pages]
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PC7410MG450NE 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays
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