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參數(shù)資料
| 型號(hào)： | PC7410 |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7410 RISC Microprocessor Product Specification |
| 中文描述： | 7410的PowerPC RISC微處理器產(chǎn)品規(guī)格 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大小： | 692K |
| 代理商： | PC7410 |
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26
PC7410
2141D–HIREL–02/04
L2 Bus AC Specifications
Table 13 provides the L2 bus interface AC timing specifications for the PC7410 as
defined in Figure 13 and Figure 14 for the loading conditions described in Figure 15.
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OV
DD
.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L2SYNC_IN (see Figure 13). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-
nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50
load (see
Figure 15).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous burst
RAMs, L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 10 is
recommended.
Figure 13.
L2 Bus Input Timing Diagram
Note:
VM = Midpoint Voltage (L2OV
DD
/2)
Table 13.
L2 Bus Interface AC Timing Specifications at V
DD
= AV
DD
= L2AV
DD
= 1.8V
±
100mV or 1.5V
±
50mV ;
-55°C
≤
T
j
≤
125°C, L2OV
DD
= 2.5V
±
100mV or L2OV
DD
= 1.8V
±
100mV
Symbol
Parameter
400, 450, 500 MHz
Unit
Min
Max
t
L2CR
& t
L2CF
(1)
L2SYNC_IN rise and fall time
1.0
ns
t
DVL2CH
(2)
Setup Times
Data and parity
1.5
ns
t
DXL2CH
(2)
Input Hold Times
Data and parity
0.0
ns
t
L2CHOV
(3)(4)
Valid Times
All outputs when L2CR[14:15] = 00
All outputs when L2CR[14:15] = 01
All outputs when L2CR[14:15] = 10
All outputs when L2CR[14:15] = 11
2.5
2.5
2.9
3.5
ns
t
L2CHOX
(3)
Output Hold Times
All outputs when L2CR[14:15] = 00
All outputs when L2CR[14:15] = 01
All outputs when L2CR[14:15] = 10
All outputs when L2CR[14:15] = 11
0.4
0.8
1.2
1.6
ns
t
L2CHOZ
L2SYNC_IN to high impedance
All outputs when L2CR[14:15] = 00
All outputs when L2CR[14:15] = 01
All outputs when L2CR[14:15] = 10
All outputs when L2CR[14:15] = 11
2.0
2.5
3.0
3.5
ns
L2SYNC_IN
L2 Data and Data
Parity Inputs
t
L2CR
t
L2CF
t
DVL2CH
t
DXL2CH
VM
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| PC7410MG450NE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
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