
17
PC7410
2141D–HIREL–02/04
Due to the complexity and the many variations of system-level boundary conditions for
today's microelectronic equipment, the combined effects of the heat transfer mecha-
nisms (radiation, convection and conduction) may vary widely. For these reasons, it is
recommended to use conjugate heat transfer models for the board, as well as system-
level designs.
To expedite system-level thermal analysis, several “compact” thermal-package models
are available within FLOTHERM
. These are available upon request.
Power Consideration
Power Management
The PC7410 provides four power modes, selectable by setting the appropriate control
bits in the MSR and HIDO registers. The four power modes are:
Full-power: This is the default power state of the PC7410. The PC7410 is fully
powered and the internal functional units are operating at the full processor clock
speed. If the dynamic power management mode is enabled, functional units that are
idle will automatically enter a low-power state without affecting performance,
software execution or external hardware.
Doze: All the functional units of the PC7410 are disabled except for the time
base/decrementer registers and the bus snooping logic. When the processor is in
doze mode, an external asynchronous interrupt, a system management interrupt, a
decrementer exception, a hard or soft reset or machine check brings the PC7410
into the full-power state. The PC7410 in doze mode maintains the PLL in a fully
powered state and locked to the system external clock input (SYSCLK) so a
transition to the full-power state takes only a few processor clock cycles.
Nap: The nap mode further reduces power consumption by disabling bus snooping,
leaving only the time base register and the PLL in a powered state. The PC7410
returns to the full-power state upon receipt of an external asynchronous interrupt, a
system management interrupt, a decrementer exception, a hard or soft reset or a
machine check input (MCP). A return to full-power state from a nap state takes only
a few processor clock cycles. When the processor is in nap mode, if QACK is
negated, the processor is put in doze mode to support snooping.
Sleep: Sleep mode minimizes power consumption by disabling all internal functional
units, after which external system logic may disable the PLL and SYSCLK.
Returning the PC7410 to the full-power state requires the enabling of the PLL and
SYSCLK, followed by the assertion of an external asynchronous interrupt, a system
management interrupt, a hard or soft reset or a machine check input (MCP) signal
after the time required to relock the PLL.