
42
PC7410
2141D–HIREL–02/04
Decoupling
Recommendations
Due to the PC7410’s dynamic power management feature, large address and data
buses and high operating frequencies, the PC7410 can generate transient power surges
and high frequency noise in its power supply, especially while driving large capacitive
loads. This noise must be prevented from reaching other components in the PC7410
system and the PC7410 itself requires a clean, tightly regulated source of power. There-
fore, it is recommended that the system designer place at least one decoupling
capacitor at each V
DD
, OV
DD
, and L2OV
DD
pin of the PC7410. It is also recommended
that these decoupling capacitors receive their power from separate V
DD
, (L2)OV
DD
, and
GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01 μF or 0.1 μF. Only ceramic SMT (surface
mount technology) capacitors should be used to minimize lead inductance, preferably
0508 or 0603 orientations where connections are made along the length of the part.
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous rec-
ommendations for decoupling PowerPC microprocessors, multiple small capacitors of
equal value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed
around the PCB, feeding the V
DD
, L2OV
DD
, and OV
DD
planes to enable quick recharging
of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent
series resistance) rating to ensure the quick response time necessary. They should also
be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors are 100 - 330 μF (AVX TPS tantalum or Sanyo OSCON).
Connection
Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an
appropriate signal level. Unused active low inputs should be tied to OV
DD
. Unused
active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected.
Power and ground connections must be made to all external V
DD
, OV
DD
, L2OV
DD
, and
GND pins of the PC7410.
See “L2 Clock AC Specifications” on page 23 for a discussion of the L2SYNC_OUT and
L2SYNC_IN signals.
Output Buffer DC
Impedance
The PC7410 60x and L2 I/O drivers are characterized over process, voltage and tem-
perature. To measure Z
0
, an external resistor is connected from the chip pad to OV
DD
or
GND. Then the value of each resistor is varied until the pad voltage is OV
DD
/2 (see Fig-
ure 31).
The output impedance is the average of two components, the resistances of the pull-up
and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and R
N
is
trimmed until the voltage at the pad equals OV
DD
/2. R
N
then becomes the resistance of
the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and R
P
is
trimmed until the voltage at the pad equals OV
DD
/2. R
P
then becomes the resistance of
the pull-up devices. R
P
and R
N
are designed to be close to each other in value. Then Z
0
= (R
P
+ R
N
)/2.