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| 型號(hào)： | PC7410 |
| 廠商： | Atmel Corp. |
| 英文描述： | PowerPC 7410 RISC Microprocessor Product Specification |
| 中文描述： | 7410的PowerPC RISC微處理器產(chǎn)品規(guī)格 |
| 文件頁(yè)數(shù)： | 28/54頁(yè) |
| 文件大?。?/td> | 692K |
| 代理商： | PC7410 |
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28
PC7410
2141D–HIREL–02/04
IEEE 1149.1 AC Timing
Specifications
Table 14
provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure
16, Figure 17, Figure 18 and Figure 19.
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK
to the midpoint of the signal in question. The output timings are measured at the pins.
All output timings assume a purely resistive 50
load (see Figure 16). Time-of-flight
delays must be added for trace lengths, vias and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes
only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization
Figure 16.
Alternate AC Test Load for the JTAG Interface
Figure 17.
JTAG Clock Input Timing Diagram
Note:
VM = Midpoint Voltage (OV
DD
/2)
Table 14.
JTAG AC Timing Specifications (Independent of SYSCLK)
(1)
at Recom-
mended Operating Conditions (see Table 4)
Symbol
Parameter
Min
Max
Unit
f
TCLK
TCK frequency of operation
0
33.3
MHz
t
TCLK
TCK cycle time
30
ns
t
JHJL
TCK clock pulse width measured at OVDD/2
15
ns
t
JR
& t
JF
TCK rise and fall times
0
2
ns
t
TRST
(2)
TRST assert time
25
ns
t
DVJH
t
IVJH
(3)
Input Setup Times:
Boundary-scan data
TMS, TDI
4
0
ns
t
DXJH
t
IXJH
(3)
Input Hold Times:
Boundary-scan data
TMS, TDI
20
25
ns
t
JLDV
t
JLOV
(4)
Valid Times:
Boundary-scan data
TDO
4
4
20
25
ns
t
JLDZ
t
JLOZ
(4)(5)
(5)
TCK to output high impedance:
Boundary-scan data
TDO
3
3
19
9
ns
Z0 = 50
RL = 50
OV
DD
/2
Output
TCLK
t
JR
t
JF
t
JHJL
t
TCLK
VM
VM
VM
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