參數(shù)資料
型號： P62000NLG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, QCC64
封裝： ROHS COMPLIANT, QFN-64
文件頁數(shù)： 6/62頁
文件大?。?/td> 1221K
代理商： P62000NLG8
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
14
IDTP62000
REV E 050510
CONFIDENTIAL
SIFDAT and SIFCLK Line Characteristics
Unless stated otherwise, VDD = 5.0 V ± 5 %, Junction Temperature = 0 to +100 °C
PAR AMET ER
SYMBOL
MIN
TYP
MAX
UNIT
Timing
SIFCLK clock frequency
FSIFCLK
500
667
833
kHz
LOW period of the SIFCLK clock
tLOW
700
875
ns
HIGH period of the SIFCLK clock
tHIGH
500
625
ns
Set-up time for a repeated START condition
tSU;STA
200
ns
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
tHD;STA
200
ns
Data hold time (pro vided when SIFDAT is output)
tHD;DAT
200
250
450
ns
Data set-up time (provided when SIFDAT is output)
tSU;DAT
200
250
ns
Rise time of both SIFDAT and SIFCLK signals
tr
5
50
ns
Fall time of both S IFDAT and SIFCLK signals
tf
5
50
ns
Set-up time for a STOP condition
tSU;STO
200
ns
Bus free time between a STOP and START condition
tBUF
500
ns
Capacitive load for each bus line
Cb
30
pF
Input parameters
Noise margin at the LOW level for each connected device
VnL
0.1 x VDD
V
Noise margin at the HIGH level for each connected device
VnH
0.2 x VDD
V
LOW level input voltage
VIL
0
0.3 x VDD
V
HIGH level input voltage
VIH
0.7 x VDD
VDD + 0.5
V
Capacitance for each I/O pin
Ci
10
pF
Output parameters
LOW level output voltage @ ± 1 mA load
VOLSIF
0.15 x VDD
V
HIGH level output voltage @ ± 1 mA load
VOHSIF
0.85 x V DD
V
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