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| 型號： | P62000NLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 50/62頁 |
| 文件大小： | 1221K |
| 代理商： | P62000NLG8 |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
54
IDTP62000
REV E 050510
CONFIDENTIAL
DEC_LEVEL3_L (Offset = 28h)
The value must be greater than DEC_LEVEL2_x if DEC is enabled. It establishes the current level which must be dropped
below for a transition from 4 phases to 3 phases to occur.
DVC Registers
DVC_CTRL (Offset = 30h)
DVC operation shall be disabled if the DVC_EN field contains 0.
DVC_WIN (Offset = 31h)
This register defines the window over which the IDTP62000 shall detect whether the load level has crossed a certain
user-defined load level. The load level must be stay over the level for at least 50% of the window period to be considered a
successful level crossing.
DVC_DFC_DELAY (Offset = 32h)
Bit
Name
Type
Default
7:5
Reserved
4:0
DEC_LEVEL3_L[4:0]
Transition current level is given by
IOCAVG * (LEVEL[4:0] + 1)/32
R/W
00x
Bit
Name
Control Function
Type
Default
7
DVC_EN
Enable DVC operation
0b =Disable
1b=Enable
If DVC_EN=1 and DVID_EN=0, then
PSI# assertions will be ignored.
R/W
0b
6:0
Reserved
Bit
Name
Control Function
Type
Default
7
Reserved
6:0
DVC_WIN[6:0]
DVC detection window, 1ms/per LSB.
This window filter is activated on when
a threshold level is crossed.
R/W
0Fx
Bit
Nam e
Control Function
Type
Default
7
Reserved
6:0
DVC_DFC_DELAY [6:0]
DVC/DFC delay time control
register. When DVC indicates that
Vcore needs to be lowered, the
DVC information is sent to the
SCPC and the timer is started
(4ms/bit). On timer completion, the
Vcore voltage is lowered.
R/W
0Fx
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