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參數(shù)資料
| 型號： | P62000NLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 30/62頁 |
| 文件大小： | 1221K |
| 代理商： | P62000NLG8 |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
36
IDTP62000
REV E 050510
CONFIDENTIAL
Figure 28: SIF Function Concept Block Diagram Inside the IDTP62000 Chip
Figure 29: SIF Function Concept Block Diagram Inside the 9CPS4592 Chip
SIF Terminology Definitions
Transmitter
The device which sends data to the bus
Receiver
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a transfer
Slave
The device or devices addressed by a master
SCPC
System Clock Power Console - 9CPS4592 with SIF to communicate with the IDTP62000
SIF: D2h, 05h, 02h
Address
Encoding/
decoding
(target device
SCPC: D2)
05h, 02h
Command
Encoding/
decoding
Data
Encoding/
decoding
02h
Load
sensing
amplifier
Internal SIF ROMtable
Reset generator
SMBUS
SIF engine
Classic Clock Generator design
IDTP62000
DFC
Threshold
comparator
OCP/OVP
detection
Register: B0, B1, B2, ,,,,
4 programmable reference level
Lv1 Lv2 Lv3 Lv4
PWM
SIF: D2h, 05h, 02h
Address
decoding
(D2)
05h, 02h
Command
decoding
Data
decoding
02h
Dynamic Frequency
Change (DFC)
process (10 stage )
DOC 1
DOC 0
10
Internal SIF ROMtable
Reset generator
PLL(s)
SMBUS
SIF engine
Classic Clock Generator design
9CPS4592
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