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| 型號： | P62000NLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 56/62頁 |
| 文件大?。?/td> | 1221K |
| 代理商： | P62000NLG8 |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
6
IDTP62000
REV E 050510
CONFIDENTIAL
Pin Descriptions
Pin #
Pin Name
Pin Type
Pin Description
1
COMP
A-I/O
Connected to the internal error amplifier. It is used with the FB pin to compensate the error
amplifier. It is the output of the error amplifier.
2
FB
A-I/O
Negative input terminal to the internal differential error amplifier. It is used with the COMP
pin to compensate the error amplifier.
3
DROOP
A-I/O
A current proportional to the total output current is sourced from this pin. Connecting this pin
to FB allows the controller to compensate output voltage droop in the output.
4
OFS
A-I/O
The OFS pin provides a means to program a DC current for generating an offset voltage
across the resistor between FB and VSENSE. The offset current is generated via an
external resistor and precision internal voltage references. The polarity of the offset is
selected by connecting the resistor to GND or VDD. For no offset, the OFS pin should be left
unconnected.
5
VSENSE
A-I
Connect directly to VCORE. It used only by the OVP and UVP blocks.
6
RGND
GND
Reference ground for the load, which is used for remote sensing to offset the internal DAC
voltage.
7
VREF
A-O
Analog output of the DAC after the DAC voltage has been referenced to RGND.
8
IREF/TCOMP_EN
A-I/O
Dual purpose pin that is used to provide:
1.Internal accurate current reference (IREF)
2.Enable for sensed load current temperature compensation (TCOMP_EN)
The reference current is provided by placing a resistor from the IREF pin to GND or VDD
with an internally generated bandgap reference voltage of 0.8 V applied across it.
Temperature compensation is enabled if the IREF resistor is tied to GND and it is disabled if
the IREF resistor is tied to VDD.
9
OSC
A-I/O
A resistor from this pin to ground selects the nominal switching frequency of the regulator.
Using 100 k
Ω will result in a switching frequency of 250 kHz.
10
PGOOD
D-O
The PGOOD signal is an active high signal that indicates whether or not the controller is
regulating the output voltage within the proper levels, and whether any fault conditions exist.
During shutdown and soft-start the PGOOD signal is pulled low and will go high after the
soft-start sequence completes and the output voltage is between the over-voltage and
under-voltage limits. (approximately 1 ms after the end of soft-start). During an
under-voltage, over-voltage, over-current condition or when the controller output enable
UVLO_PVCC is pulled low, PGOOD will go low. Moreover, PGOOD will also be pulled low
when a no-CPU VID (or OFF) code is selected or during any reset event.
11
UVLO_PVCC
A-I
Pin should be externally connected to a resistor divider between PVCC and GND. It is used
to detect that the PVCC level has come up. When the voltage at the pin rises above its
threshold (0.8V) then the internal power on reset is released provided that the internal VDD
based POR level has been also reached. It is recommended that the user bias this pin with
a resistor divider that generates the POR threshold voltage when PVCC is at 2/3 of its
maximum value.
12
UVLO_VTT
A-I
Another threshold-sensitive enable input for the controller. It's typically connected to the VTT
output of the VTT voltage regulator in the computer mother board.
13
SS/SMBA0
A-I/O
Multiple purpose pin. One of its functions is to set the soft start ramp slope for the Intel DAC
modes of operation by a resistor connected to ground. The pin also determines the value of
the SMBus address A0 bit. The A0 logic level is determined by the level on this pin at power
up. If the resistor is connected to VDD, the A0 bit is set to high. If the resistor is connected
GND, the A0 bit is set to low.
14
PSI#
A-I
The power state indicator mode pin (PSI#) is a logical input to initiate a phase dropping
scheme for higher efficiency at light load. The input conforms to the 1.2 V CMOS levels
defined in the VRD11.1 specification (nominally 1.2v high, 0v low).
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