參數(shù)資料
型號: P62000NLG8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, QCC64
封裝: ROHS COMPLIANT, QFN-64
文件頁數(shù): 43/62頁
文件大?。?/td> 1221K
代理商: P62000NLG8
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
48
IDTP62000
REV E 050510
CONFIDENTIAL
VID Code Registers
VID_CTRL (Offset = 04h)
VID_DAC_STAT (Offset = 05h)
This register is always loaded by transferring the value from the VID_INPUT_STAT register (based on the DVID_EN field of
the VID_CTRL CSR register), and indicates the VID code currently being used by the DAC. It does not include the effect of
any offsets induced by enabling the VID_OFFSET_EN field in the VID_CTRL CSR register.
VID_INPUT_STAT (Offset = 06h)
This register is written by either the external VID[7:0] pins or by a CSR write, depending on the value of
VID_CSR_WRITE_EN in the DEV_CTRL2 register.
Bit
Name
Control Function
Type
Default
7:6
VID_MODE[1:0]
Voltage regulator mode
00b = VR10
01b = VR11
10b = AMD PVI
11b = AMD SVI
This bit may not be wri tten unless
VID_CSR_WRITE_EN = 1b
R/W or
RO
Defined by
VID_SEL
and VID[1]
pins
5
DVID_EN
Dynamic VID control enable
If high, then changes to the
VID_INPUT_STAT register are
copied to the VID_DAC_STAT
register. If low, the VID_DAC_STAT
register cannot be changed.
When this bit is low and DVC mode is
enabled, then the PSI input will be
ignored (since the DAC input codes
cannot be updated).
R/W
1b
4
VID_OFFSET_EN
VID offset adjustment enable
When DVC_EN=1b then regardless of
the value contained in this register, the
VID_OFFSET will never be enabled.
R/W
0b
3:0
Reserved
Bit
Nam e
Type
Default
7:0
VID_DAC[7:0]
Current VID input setting of DAC
RO
00b
Bit
Nam e
Type
Default
7:0
VID_INPUT[7:0]
Loaded VID setting
This field may not be written
unless VID_CSR_WRITE_EN = 1b
R/W or
RO
Defined by
VID[7:0]
pins
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