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參數(shù)資料
| 型號： | P62000NLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 19/62頁 |
| 文件大?。?/td> | 1221K |
| 代理商： | P62000NLG8 |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
26
IDTP62000
REV E 050510
CONFIDENTIAL
Input Under Voltage and Enable/Disable
The IDTP62000 is enabled once the voltage on the VDD, UVLO_PVCC, and UVLO_VTT pins exceed their thresholds. The
VDD threshold is fixed but the UVLO_PVCC and UVLO_VTT thresholds can be programmed with a resistor divider. In most
applications UVLO_PVCC will monitor the 12V input while UVLO_VTT is used as the converter Enable input. Any sequence
of 5V and 12V input supplies is acceptable.
Deassertion of VDD, UVLO_PVCC, or UVLO_VTT pins will result in converter shutdown. If VDD is deasserted all digital
registers will revert to their default settings. Deassertion of either UVLO_PVCC or UVLO_VTT will reset the SMBus status
registers only. Figure 21 provides a block diagram of the Input under voltage and enable functions.
Figure 21: Input Under Voltage and Enable Block Diagram
Soft-Start and SMBus Address Programming
The soft-start function of the IDTP62000 enables a smooth charge of the output capacitors in order to limit the inrush input
current during startup. The soft-start function is enabled approximately 1 ms after Enable. The SS/SMBA0 pin also
determines the value of the SMBus address A0 bit. Connect a resistor from the SS/SMBA0 pin to either VDD or ground. If
the resistor is connected to VDD, the A0 bit is set to high. If the resistor is connected to ground, the A0 bit is set to low.
Intel Soft-Start
In Intel modes, the soft-start ramp is set by the RSS resistor. The IDTP62000 regulates the voltage across the resistor to
0.8V.Output voltage first ramps to Vboot and waits for a period of time, T3, (approximately 100 s). It then ramps to the value
determined by the active VID code. Equation 9 determines soft start rate frequency of each 6.25 mV step. The range of RSS
is 25 to 250 kohm.
FSS = 25x10
6 / R
SS kHz (equation 9)
The complete Intel mode soft start sequence is depicted in Figure 22. The POR signal occurs when all 3 enable inputs
become valid.
OSC
09
EN
Power on
Reset Logic
0.8V
UVLO_VTT
UVLO_PVCC
VDD (Pins
23 & 57)
12
11
nn
0.8V
Channel
Detection
3-4 Phase
Fault Detect
& Sync
Control
Ramp
Generation
Control &
Clocks
OV
OC
+
-
+
-
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