參數(shù)資料
型號(hào)： P62000NLG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, QCC64
封裝： ROHS COMPLIANT, QFN-64
文件頁(yè)數(shù)： 22/62頁(yè)
文件大?。?/td> 1221K
代理商： P62000NLG8
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
29
IDTP62000
REV E 050510
CONFIDENTIAL
Figure 24: Power Good Function
Under Voltage Detection
The VSENSE pin provides ultra-fast under voltage detection. An under voltage event occurs when the output voltage falls
below 60% of the target VID code voltage. The VID code voltage is represented by the voltage present at the VREF pin. UVD
detection is blanked during a D-VID/DVC operation so as not to give false triggers. During an UVD event the PGOOD pin
will be low, thus indicating that a fault condition in the system exists.
Overvoltage Detection
An overvoltage condition is defined as when the output voltage coming from the PWM is higher than the OVP level for more
than 250 ns. The trip level value is dependent on which mode of operation the PWM is in. A dedicated VSENSE pin is used
to enable ultra-fast response. In Intel mode, the OVP level depends on whether it's in normal running mode or if it's in the
pre/post soft-start cycle.
During the boot period but prior to the soft-start cycle (before the completion of TC) the OVP trip_level is set to ~1.35 V
(nominal 1.1 V + 250 mV OVP_OFFSET). During the time between the boot period and when PGOOD is asserted, the
trip_voltage will equal the greater of the boot period trip voltage or the normal operation trip_level.
During normal operation, the OVP trip level is set to the voltage of the DAC output (VREF) plus OVP_OFFSET.
It is critical for the OVP circuitry to respond quickly and accurately to an over voltage condition. Even a small time exposure
to high voltages could easily cause damage to sub-micron geometry processes such as a 32 nm CPU. If an over-voltage
condition is detected (either during normal operation or during soft start) the controller will switch on all low-side power
MOSFETs and switch off all the high-side MOSFETs in order to protect the load. If the OVP event occurs during normal
operation executing a power cycle or performing a reset will be required to restart the controller. If the OVP event occurs
during soft start and the part is in Intel mode, the OVP event will not be latched. Instead, the controller will bias the power
MOSFETs as described above until the OVP condition disappears, and then will begin the soft start sequence again.
Pre-POR Overvoltage Protection
DAC
VREF
+250
mV
60
%
Over Current
Protection
IP
H1
IP
H2
IP
H3
IP
H4
IA
V
IR
E
F
x
GND
PGOOD
IMONOV
10
15
05
07
Ov
e
r
Vo
ltag
e
De
te
ct
U
nde
r
Vo
ltag
e
De
te
ct
OV
UV
OC
EN
06
Power on Reset
Logic
0.8V
UVLO_VTT
UVLO_PVCC
VDD
12
11
23
RGND
VSENSE
+
-
+
-
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