參數(shù)資料
型號(hào)： P62000NLG8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, QCC64
封裝： ROHS COMPLIANT, QFN-64
文件頁(yè)數(shù)： 54/62頁(yè)
文件大?。?/td> 1221K
代理商： P62000NLG8
IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
58
IDTP62000
REV E 050510
CONFIDENTIAL
Glossary
Term
Description
AVP
Adaptive Voltage Positioning
CSR
Command and Status Register
DCR
Direct Current Resistance
DEC
Dynamic Efficiency Control
DFC
Dynamic Frequency Change
DVC
Dynamic Voltage Change
D-VID
Dynamic Voltage Identification. A low power mode of operation where the processor instructs the VRD to operate at a lower
voltage.
ESL
Equival ent Series Inductance
ESR
Equival ent Series Resistance
Icc
Processor current
Itt
Bus current associated with the Vtt supply
Load Line
A mathematical model that describes voltage current relationship given system impedance (RLL). The load line equati ons is
Vcc= VID – I*RLL. In this document, the load line is referenced at the socket unless otherwise stated.
NTC
Negative Thermal Coefficient
OCP
Over-current protection
OVP
Over-voltage protection
PROCHOT#
Under thermal monitoring, the VRD asserts this processor input to indicate an over-temperature condition has occurred.
Assertion of this signal places the processor in a low power state, thereby cooling the voltage regulator.
PVI
AMD K8 Parallel VID interface
PWM
Pulse Width Modulation
RDS-ON
FET source to drain channel resistance when bias on.
RLL
Load line impedance. Defined as the ra tio: Voltage droop/current step. This is the load line slope.
SCPC
System Clock Power Console
SIF
Serial interface to SCPC chip
Static Load Line
DC resistance at the defined regulation node. Defined as the quotient of voltage and current (V/I) under steady state
condi tions. This value is configured by proper tuning of the PWM controller voltage positioning circuit.
SVI
AMD K8 Serial VID Interface
Thermal Monitor
A feature of the voltage regulator that places the processor in a low power state when critical VRD temperatures are reached,
thereby redu cing power and VRD temperature.
TOB
Vcc regulation tolerance band. Defines the voltage regulator’s 3-σ voltage variation across temperature, manufacturing
variation, and aging factors. Must be ensured by design through component selection. Defined at proce ssor maximum
current and maximum VID levels.
Transient Load Line
Equal to dV/di or Vdroop/Istep and is controlled by switching frequency, decoupling capacitor selection, motherboard layout
parasitics.
VCORE
Processor core voltage identification defined in the processor datasheet.
VID
Voltage Identification:
1. A code supplied by the processor that determines the reference output voltage to be delivered to the processor VCORE
lands. 2. VID is the voltage at the processor at zero amperes and the tolerance band at + 3-σ.
VR_TDC
Voltage Regulator Thermal Desig n Current. The sustained DC current which the voltage regulator must support under the
system defined cooling solution.
VRD
Voltage regulator down. A VR ci rcuit resident on the motherboard.
VRDn
The Intel voltage reference specification level n.
VRM
Voltage regulator module that is socketed to a motherboard.
Vtt
Voltage provided to the processor to initiate power up and drive I/O buffer circuits.
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