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參數(shù)資料
| 型號： | P62000NLG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, QCC64 |
| 封裝： | ROHS COMPLIANT, QFN-64 |
| 文件頁數(shù)： | 17/62頁 |
| 文件大小： | 1221K |
| 代理商： | P62000NLG8 |
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IDTP62000
2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
IDT 2/3/4-PHASE PWM CONTROLLER WITH DYNAMIC VOLTAGE & FREQUENCY SCALING
24
IDTP62000
REV E 050510
CONFIDENTIAL
Dynamic Voltage Change
The IDTP62000 incorporates a feature whereby the VCORE voltage can be dynamically changed based on the sensed load
current. It also supports the existing DFC capability of the clock generator design.
There are four DFC states available in the 9CPS4592 clock generator design. IDTP62000 has four DVC states to match the
9CPS4592. The controller compares the sensed dynamic load current of the processor and compares this sensed level with
three load thresholds (DVC_LEVEL) that are register programmed through the SMBUS. As shown in Figure 17, each
threshold has one value for rising currents (called “H” for high) and another for falling currents (called “L” for low), so that
hysteresis can be implemented in DVC level changes. In addition, each DVC level has an associated register programmed
VID code offset value.
The DVC function of IDTP62000 combined with the 9CPS4592 DFC function in a system provides a solution for system
design to have optimal performance enhancement and power saving features.
Output-Voltage Offset Programming
Converter output voltage can be offset either higher or lower than the VID voltage. If a resistor is connected between the
OFS pin and Vdd the IDTP62000 regulates the voltage across the resistor to 1.6 V. The resulting current is mirrored and will
flow from FB pin to ground creating a positive off set in converter output voltage. If a resistor is connected between the OFS
pin and ground the voltage across the resistor is regulated to 0.4V and the resulting current is mirrored into the FB pin
creating a negative offset voltage. The max offset voltage in either direction is 150A multiplied by the resistance of RFB. If
the OFS pin is left floating then no offset is applied. Equations 7 and 8 describe pin programming of offset voltage. Offset
voltage can also be programmed using the SMBus. This works by modifying the VID code and adjusting the under voltage
and over voltage thresholds accordingly
Voffset (+) = RFB x (VDD - 1.6) / ROFS (equation 7)
Voffset (-) = RFB x 0.4 / ROFS (equation 8)
DVC Programming
The DVC registers should only be programmed when the DVC mode is disabled i.e. when the DVC_EN bit of the DVC_CTRL
register is low. By default, the DVC feature is disabled. It can be enabled by setting the DVC_EN bit to high in the DVC_CTRL
register.
Sensed Load Current Thresholds and Filters
IDTP62000 has four output voltage offset values which are delineated by three pairs of sensed load current levels. Each
level has user programmable upper and lower threshold level that facilitates the addition of hysteresis. The threshold levels
and offsets are illustrated below. When a threshold crossing has been detected, the filter timer DVC_WIN is initiated. The
current level has to stay above (or below) the threshold for at least 50% of the timer duration in order for it to be recognized
as a DVC trigger event. All DVC levels are defined as a percentage of the average phase current level that triggers an
over-current condition (IOCAVG), and are given by IOCAVG*(LEVEL[4:0] + 1)/32.
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