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參數(shù)資料
| 型號： | MT9LD272 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Meg x 72 Buffered DRAM DIMMs(2M x 72緩沖動態(tài)RAM模塊（雙列直插存儲器模塊）) |
| 中文描述： | 2Meg × 72緩沖內(nèi)存插槽（200萬× 72緩沖動態(tài)內(nèi)存模塊（雙列直插存儲器模塊）） |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MT9LD272 |
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2, 4 Meg x 72 Buffered DRAM DIMMs
DM33.p65 – Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
5
2, 4 MEG x 72
BUFFERED DRAM DIMMs
OBSOLETE
PIN DESCRIPTIONS
PIN NUMBERS
30, 45
SY MBOL
RAS0#, RAS2#
TY PE
Input
DESCRIPTION
Row-Address Strobe: RAS# is used to clock-in the row-
address bits. Two RAS# inputs allow for one x72 bank
or two x36 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. WE0# controls DQ0-DQ35. WE2# controls
DQ36-DQ71. If WE# is LOW prior to CAS# going LOW,
the access is an EARLY WRITE cycle. If WE# is HIGH
while CAS# is LOW, the access is a READ cycle,
provided OE# is also LOW. If WE# goes LOW after
CAS# goes LOW, then the cycle is a LATE WRITE cycle.
A LATE WRITE cycle is generally used in conjunction
with a READ cycle to form a READ-MODIFY-WRITE
cycle.
Output Enable: OE# is the input/output control for the
DQ pins. OE0# controls DQ0-DQ35. OE2# controls
DQ36-DQ71. These signals may be driven, allowing
LATE WRITE cycles.
Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#. A0 is common to the
DRAMs used for DQ0-DQ35 while B0 is common to the
DRAMs used for DQ36-DQ71
Data I/O: For WRITE cycles, DQ0-DQ71 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ71 act as outputs for the addressed DRAM
location.
28, 46
CAS0#, CAS4#
Buffered
Input
27, 48
WE0#, WE2#
Buffered
Input
31, 44
OE0#, OE2#
Buffered
Input
33-38, 117-122, 126
A0-A11, B0
Buffered
Input
2-5, 7-11, 13-17, 19-22,
52-53, 55-58, 60, 65-67,
69-72, 74-77, 86-89,
91-95, 97-101, 103-106,
136-137, 139-142,
144, 149-151, 153-156,
158-161
79-82, 163-166
DQ0-DQ71
Input/
Output
PD1-PD8
Buffered
Output
Presence-Detect: These pins are read by the host system
and tell the system the DIMM’s personality. They will be
either no connect (1), or they will be driven to V
OL
(0).
Reserved for Future Use: These pins should be left
unconnected.
29, 41-42, 47, 61-64, 111,
113, 115, 125, 128, 131,
145-148
6, 18, 26, 40, 49, 59, 73,
84, 90, 102, 110, 124,
133, 143, 157, 168
1, 12, 23, 32, 43, 54,
68, 78, 85, 96, 107, 116,
127, 138, 152, 162
83, 167
RFU
–
V
DD
Supply
Power Supply: +3.3V ± 0.3V.
V
SS
Supply
Ground.
ID0, ID1
Output
ID Bits: ID0 = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (V
SS
).
Presence-Detect Enable: PDE# is the READ control for
the buffered presence-detect pins.
132
PDE#
Input
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT9LD272A | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2, 4 MEG x 72 NONBUFFERED DRAM DIMMs |
| MT9LD272AG-52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
| MT9LD272AG-5X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| MT9LD272AG-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Fast Page Mode DRAM Module |
| MT9LD272AG-60B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
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