參數(shù)資料
型號: MT9LD272
廠商: Micron Technology, Inc.
英文描述: 2Meg x 72 Buffered DRAM DIMMs(2M x 72緩沖動態(tài)RAM模塊(雙列直插存儲器模塊))
中文描述: 2Meg × 72緩沖內(nèi)存插槽(200萬× 72緩沖動態(tài)內(nèi)存模塊(雙列直插存儲器模塊))
文件頁數(shù): 10/29頁
文件大?。?/td> 491K
代理商: MT9LD272
2, 4 Meg x 72 Buffered DRAM DIMMs
DM33.p65 – Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
10
2, 4 MEG x 72
BUFFERED DRAM DIMMs
OBSOLETE
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 35) (V
DD
= +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
PDE# to valid presence-detect data
PDE# inactive to presence-detects inactive
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (2,048 cycles) (16MB)
Refresh period (4,096 cycles) (32MB)
RAS# precharge time
RAS# to CAS# precharge time
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
WRITE command pulse width
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
-6
SYMBOL
t
PD
t
PDOFF
t
PRWC
t
RAC
t
RAD
t
RAH
t
RAS
t
RASP
t
RC
t
RCD
t
RCH
t
RCS
t
REF
t
REF
t
RP
t
RPC
t
RRH
t
RSH
t
RWC
t
RWD
t
RWL
t
T
t
WCH
t
WCR
t
WCS
t
WP
t
WRH
t
WRP
MIN
MAX
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
32
31
21
13
17, 24
22
2
87
60
13
8
60
60
110
18
2
2
10,000
125,000
16, 24
18, 21
21
32
64
40
0
0
20
160
87
20
2
15
43
2
10
8
12
18
23
23
21, 28
23
50
23
22
21, 28
22
21
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參數(shù)描述
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