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參數(shù)資料
| 型號： | MT9LD272 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Meg x 72 Buffered DRAM DIMMs(2M x 72緩沖動態(tài)RAM模塊（雙列直插存儲器模塊）) |
| 中文描述： | 2Meg × 72緩沖內(nèi)存插槽（200萬× 72緩沖動態(tài)內(nèi)存模塊（雙列直插存儲器模塊）） |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MT9LD272 |
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2, 4 Meg x 72 Buffered DRAM DIMMs
DM33.p65 – Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
2
2, 4 MEG x 72
BUFFERED DRAM DIMMs
OBSOLETE
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT9LD272G-x X
MT18LD472G-x X
MT18LD472FG-x X
x = speed
CONFIGURATION
2 Meg x 72 ECC
4 Meg x 72 ECC
4 Meg x 72 ECC
REFRESH
2K Refresh
2K Refresh
4K Refresh
FPM Operating Mode
PART NUMBER
MT9LD272G-x
MT18LD472G-x
MT18LD472FG-x
x = speed
CONFIGURATION
2 Meg x 72 ECC
4 Meg x 72 ECC
4 Meg x 72 ECC
REFRESH
2K Refresh
2K Refresh
4K Refresh
GENERAL DESCRIPTION
The MT9LD272(X ) and MT18LD472(F)(X ) are ran-
domly accessed 16MB and 32MB memories organized
in a x72 configuration. They are specially processed to
operate from 3V to 3.6V for low-voltage memory
systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits. Two copies of
address 0 (A0 and B0) are defined to allow maximum
performance for four-byte applications which inter-
leave between two four-byte banks. A0 is common to
the DRAMs used for DQ0-DQ35, while B0 is common
to the DRAMs used for DQ36-DQ71. RAS# is used to
latch the first 11/12 bits and CAS# the latter 10/11 bits.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE oc-
curs when WE# falls after CAS# was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of OE#. During
LATE WRITE or READ-MODIFY-WRITE cycles, OE#
must be taken HIGH to disable the data-outputs prior
to applying input data. If a LATE WRITE or READ-
MODIFY-WRITE is attempted while keeping OE# LOW,
no WRITE will occur, and the data-outputs will drive
read data from the accessed location.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data
operations (READ or WRITE) within a row-address-
defined page boundary. The FAST-PAGE-MODE cycle
is always initiated with a row address strobed in by
RAS#, followed by a column address strobed in by
CAS#. Additional columns may be accessed by provid-
ing valid column addresses, strobing CAS# and hold-
ing RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGE-
MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the “X ” version,
is an accelerated FAST-PAGE-MODE cycle. The pri-
mary advantage of EDO is the availability of data-out
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (
t
CP) to occur without the out-
put data going invalid. This elimination of CAS#
output control provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE#
is pulsed while RAS# and CAS# are LOW, data will
toggle from valid data to High-Z and back to the same
valid data. If OE# is toggled or pulsed after CAS# goes
HIGH while RAS# remains LOW, data will transition
to and remain High-Z.
During an application, if the DQ outputs are wire
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also High-Z the outputs. Inde-
pendent of OE# control, the outputs will disable after
t
OFF, which is referenced from the rising edge of RAS#
or CAS#, whichever occurs last. (Refer to the 4 Meg x 4
[MT4LC4M4E8] DRAM data sheet for additional in-
formation on EDO functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and ex-
ecuting any RAS# cycle (READ, WRITE) or RAS# RE-
FRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses are executed at least
every
t
REF, regardless of sequence. The CBR REFRESH
cycle will invoke the internal refresh counter for auto-
matic RAS# addressing.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9LD272A | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2, 4 MEG x 72 NONBUFFERED DRAM DIMMs |
| MT9LD272AG-52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
| MT9LD272AG-5X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| MT9LD272AG-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Fast Page Mode DRAM Module |
| MT9LD272AG-60B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
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