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參數資料
| 型號： | MT9LD272 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Meg x 72 Buffered DRAM DIMMs(2M x 72緩沖動態(tài)RAM模塊（雙列直插存儲器模塊）) |
| 中文描述： | 2Meg × 72緩沖內存插槽（200萬× 72緩沖動態(tài)內存模塊（雙列直插存儲器模塊）） |
| 文件頁數： | 14/29頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MT9LD272 |
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2, 4 Meg x 72 Buffered DRAM DIMMs
DM33.p65 – Rev. 2/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
14
2, 4 MEG x 72
BUFFERED DRAM DIMMs
OBSOLETE
NOTES (continued)
31.
t
PDOFF MAX is determined by the pull-up resistor
value. Care must be taken to ensure adequate
recovery time prior to reading valid up-level on
subsequent DIMM position.
32.Measured with specified current load and 100pF.
33.With the FPM option,
t
OFF is determined by the
first RAS# or CAS# signal to transition HIGH. In
comparison,
t
OFF on an EDO option is deter-
mined by the latter of the RAS# and CAS# signals
to transition HIGH.
34.Applies to both FPM and EDO operating modes.
35.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
possible.
36. V
IH
overshoot: V
IH
(MAX ) = V
DD
+ 2V for a pulse
width
￡
10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
￡
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MT9LD272A | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2, 4 MEG x 72 NONBUFFERED DRAM DIMMs |
| MT9LD272AG-52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
| MT9LD272AG-5X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| MT9LD272AG-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Fast Page Mode DRAM Module |
| MT9LD272AG-60B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
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