參數(shù)資料
型號(hào): MT90883
廠商: Zarlink Semiconductor Inc.
英文描述: TDM to Packet Processors
中文描述: TDM到分組處理器
文件頁(yè)數(shù): 80/97頁(yè)
文件大?。?/td> 702K
代理商: MT90883
MT90880/1/2/3
Data Sheet
80
Zarlink Semiconductor Inc.
8.2 Recommendation
This device should not be used in a half-duplex network application. The final link to the device should be as short
as possible, (for example from an Ethernet Switch), in order to minimise the probability of corrupted packets on the
link.
9.0 DC Characteristics
Note: Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.
The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V
during power-up. Failure to observe this rule could lead to a high-current latch-up state, possibly leading to chip
failure, if sufficient cross-supply current is available. To be safe ensure the I/O supply voltage supply always rises
earlier than the core and PLL supply voltages.
Absolute Maximum Ratings -
Voltage measurements are with respect to ground (V
SS
) unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
I/O Supply Voltage
V
DD_IO
-0.5
5.0
V
Core Supply Voltage
V
DD_CORE
-0.5
2.5
V
PLL Supply Voltage
V
DD_PLL
-0.5
2.5
V
Input Voltage
V
I
-0.5
V
DD
+ 0.5
V
Input Voltage (5 V tolerant inputs)
V
I_5 V
-0.5
7.0
V
Continuous current at digital inputs
I
IN
-
±
10
mA
Continuous current at digital outputs
I
O
-
±
15
mA
Package power dissipation
PD
-
4
W
Storage Temperature
TS
-55
+125
°
C
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