參數(shù)資料
型號(hào)： MT90883
廠(chǎng)商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁(yè)數(shù)： 77/97頁(yè)
文件大小： 702K
代理商： MT90883
MT90880/1/2/3
Data Sheet
77
Zarlink Semiconductor Inc.
Two factors affect the frequency stability while in Holdover. The first factor is the drift on the master clock
(S_CLK) frequency. Any drift in master clock frequency translates directly into drift on the holdover frequency.
Note that the absolute master clock accuracy does not affect the stability of the held frequency, only changes in
the master clock frequency while in holdover mode. For example, a 32 ppm master clock may have a
temperature coefficient of 0.1 ppm/
0
C. So, a 10
0
C change in temperature may result in an additional frequency
offset of 1 ppm, over and above the intrinsic accuracy of 0.06 ppm.
The second factor affecting stability is any large frequency jitter on the reference input prior to the reference
failure. This could cause the measured frequency to be inaccurate, resulting in an incorrect holdover frequency.
Jitter Transfer
In master mode, jitter on the incoming reference is attenuated by both a Phase Slope Limiter and the internal
Loop Filter. The Phase Slope Limiter limits the output phase slope to 7 ns per 125
μ
s. Therefore, even if the
phase slope of the input signal exceeds this rate, such as for low frequency input jitter with a very large
amplitude, the maximum output phase slope will be limited to 7 ns per 125
μ
s. The internal loop filter is a single
pole low-pass filter with a cutoff frequency of 1.25 Hz. This progressively attenuates all jitter above the cutoff
frequency at a rate of 20 dB/decade.
Figure 36 shows the DPLL jitter transfer function diagram across a wide range of frequencies, while Figure 37 is
the portion of the diagram from Figure 36 around 0dB of the jitter transfer amplitude. From this diagram it is
possible to see that the DPLL is a second order, type 2 PLL.
Figure 36 - DPLL Jitter Transfer Function Diagram Across a Wide Range of Frequencies
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90883A 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883A/IG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883BP1N 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883IG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT9088IG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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