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參數(shù)資料
| 型號(hào)： | MT90883 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 34/97頁 |
| 文件大小： | 702K |
| 代理商： | MT90883 |
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MT90880/1/2/3
Data Sheet
34
Zarlink Semiconductor Inc.
Packet Interface to PCI Interface
Similarly, packets destined for the host CPU or other PCI devices can be sent over the packet network to the
PCI device. The headers of incoming packets are parsed by the Packet Classifier, and can be directed to one of
four queues pointing towards the PCI interface. The classifier can be set-up so that each queue is dedicated to
a specific device or application flow.
Figure 16 - Packet to PCI Data Flow
5.4 Packet Assembly
The incoming TDM data streams are assembled into packet payloads by the WAN Receive block. This can handle
up to 128 active contexts at a time, where each context represents a “virtual channel connection” in CES terms.
Each context generates a single stream of packets, identified by a label in the packet header known as the "context
ID".
A context may contain any number of 64 Kbs channels. These channels need not be contiguous, and in
synchronous mode they can be selected from any input stream. In asynchronous mode each stream is
independently clocked, which can result in phase and frequency differences between streams. Therefore, in this
mode contexts may only contain channels from a single stream.
Channels may be added or deleted dynamically from a context. This feature can be used to optimize bandwidth
utilization. Modifications to the context are synchronized with the start of a new packet.
5.4.1 Payload Order
Packets are assembled sequentially, with each channel placed into the packet as it arrives at the WAN Access
Interface. A fixed order of streams and channels is maintained (see Figure 17), with channel 0, stream 0 placed
before channel 0, stream 1, which is placed before channel 1, stream 0. It is this order that allows the packet to be
correctly disassembled at the far end.
Data Flow
Control Flow
W
P
Packet Memory
Host Processor
相關(guān)PDF資料 |
PDF描述 |
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| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
| MT91600AN1 | Programmable SLIC |
| MT91600ANR | Programmable SLIC |
| MT91600ANR1 | Programmable SLIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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