參數(shù)資料
型號: MT90883
廠商: Zarlink Semiconductor Inc.
英文描述: TDM to Packet Processors
中文描述: TDM到分組處理器
文件頁數(shù): 17/97頁
文件大?。?/td> 702K
代理商: MT90883
MT90880/1/2/3
Data Sheet
17
Zarlink Semiconductor Inc.
Table 8 - PCI Interface
3.5 External Memory Interface
The external memory signals are
NOT
5 V tolerant.
Active low signals are designated by a # suffix, in accordance with the convention used in common memory
data sheets
Table 9 - External Memory Interface
pci_trdy#
I O
AA23
PCI target ready
pci_irdy#
I O
AF26
PCI initiator ready
pci_stop#
I O
AC24
PCI stop
pci_devsel#
I O
AE26
PCI device select
pci_idsel
I
AB20
PCI ID select
pci_perr#
I O
AD26
PCI parity error
pci_serr#
I O
AB24
PCI system error (NOT open drain.
See “Open Drain Circuitry” on
page 71)
pci_lock#
I O
Y22
PCI lock. Refer to PCI spec section
2.2.3
pci_inta#
I O
AF19
PCI interrupt (NOT open drain. See
“Open Drain Circuitry” on page 71)
PCI_M66EN
I O
Y25
33 MHz /66 MHz select
Signal
I/O
Package Balls
Description
ram_d[31:0]
IOU
N2 [31], R4 [30], N1 [29], R5 [28],
P1 [27], T4 [26], P2 [25], P3 [24],
R1 [23], AB4 [22], AC2 [21], AD1 [20],
AC3 [19], AD2 [18], AC4 [17], AE1 [16],
AE2 [15], AD3 [14], AC5 [13], AF1 [12],
AF2 [11], AC6 [10], AE3 [9], AF3 [8],
AD4 [7], AB7 [6], AE4 [5], AF4 [4],
AD5 [3], AC7 [2], AE5 [1], AB8 [0]
Buffer memory data
ram_a[22:2]
O
T5 [22], R3 [21], U4 [20],
T1 [19], U5 [18], T2 [17], T3 [16],
U1 [15], U2 [14], U3 [13], V4 [12],
V1 [11], V5 [10], V2 [9], W4 [8],
W1 [7], W2 [6], Y1 [5], W5 [4],
W3 [3], Y4 [2]
Buffer memory address
(up to 8 MBytes)
ram_adsc#
O U
AB3
Buffer memory address status control
ram_we[3:0]#
O U
Y5 [3], AA1 [2], Y3 [1], AA2 [0]
Buffer memory write chip select
ram_oe[3:0]#
O U
AB1 [3], AA4 [2], AB2 [1], AC1 [0]
Buffer memory read chip select
Signal
I/O
Package Balls
Description
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