參數(shù)資料
型號： MT90883
廠商： Zarlink Semiconductor Inc.
英文描述： TDM to Packet Processors
中文描述： TDM到分組處理器
文件頁數(shù)： 15/97頁
文件大小： 702K
代理商： MT90883
MT90880/1/2/3
Data Sheet
15
Zarlink Semiconductor Inc.
3.3.2 RMII Interfaces
The RMII is a low pin count MII interface. It has no defined standard, but the RMII Consortium publishes details
(reference 3, Table 2). The MT90880 RMII Interface shares the same pins as the MII interface with the
exception of the REF_CLK.
The RMII comprises a low pin count Reduced Media Independent Interface
TM
(RMII
TM
)
specification intended for
use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3u [2] an MII, comprised of 16 pins for data
and control, is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of
pins can add significant cost as the port counts increase. The purpose of this interface is to provide a low cost
alternative to the IEEE 802.3u [2] MII. Architecturally, the RMII specification provides for an additional
reconciliation layer on either side of the MII but can be implemented in the absence of an MII. The management
interface (MDIO/MDC) is assumed to be identical to that defined in IEEE 802.3u [2].
All RMII signals are 5 V tolerant.
All RMII outputs are high impedance while S_RST is low.
m0_txclk
I U
AB9
Transmit clock
m0_rxd[3:0]
I U
AF8 [3], AE8 [2], AE9 [1], AD9 [0]
Receive data
m0_rxdv
I D
AF7
Receive data valid
m0_rxclk
I U
AB10
Receive clock
m0_rxer
I D
AD8
Receive error
m0_crs
I D
AC9
Carrier sense
m0_col
I D
AE7
Collision detect
MII Port B
m_mint1
I U
AE11
MII management interrupt for port B
m1_txd[3:0]
O U
AC11 [3], AE10 [2], AF10 [1], AD11
[0]
Transmit data
m1_txen
O U
AD10
Transmit enable
m1_txclk
I U
AB12
Transmit clock
m1_rxd[3:0]
I U
AF12 [3], AD13 [2], AE13 [1], AF13
[0]
Receive data
m1_rxdv
I D
AE12
Receive data valid
m1_rxclk
I U
AC13
Receive clock
m1_rxer
I D
AD12
Receive error
m1_crs
I D
AC12
Carrier sense
m1_col
I D
AF11
Collision detect
Signal
I/O
Package Balls
Description
Table 6 - MII Interfaces (continued)
相關(guān)PDF資料
PDF描述
MT91600 Programmable SLIC
MT91600AN Programmable SLIC
MT91600AN1 Programmable SLIC
MT91600ANR Programmable SLIC
MT91600ANR1 Programmable SLIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90883A 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883A/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90883IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT9088IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*