- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359235 > MT90883 (Zarlink Semiconductor Inc.) TDM to Packet Processors PDF資料下載
參數(shù)資料
| 型號(hào)： | MT90883 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁(yè)數(shù)： | 14/97頁(yè) |
| 文件大?。?/td> | 702K |
| 代理商： | MT90883 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)
MT90880/1/2/3
Data Sheet
14
Zarlink Semiconductor Inc.
3.3 Packet Interfaces
3.3.1 MII Interfaces
Data for the MII packet switching is based on Specification IEEE Std 802.3u – 1995. The MII has separate
transmit and receive circuits, and consequently the characteristics are shown in the relevant tables.
All MII signals are 5 V tolerant.
All MII outputs are high impedance while S_RST is low.
LOC_STO [7:0]
O
L5 [7], L4 [6], K2 [5], L3 [4],
L2 [3], P4 [2], M2 [1], N3 [0]
Local TDM interface serial output
streams
Operate at 2.048, 4.096 and 8.192 Mbs
MT90880 variant only
c4ob
O
B8
TDM interface 4.096 MHz clock
All variants
fp4ob
O
C8
8 KHz frame pulse for C4OB clock
All variants
c8ob
O
A7
TDM interface 8.192 MHz clock
All variants
fp8ob
O
A6
8 KHz frame pulse for C8OB clock.
All variants
c16ob
O
B7
TDM interface 16.384 MHz clock
All variants
fp16ob
O
D8
8 KHz frame pulse for C16OB clock.
All variants
ode
I D
A8
WAN and TDM serial output enable. High
to enable outputs, low for high
impedance.
All variants
Signal
I/O
Package Balls
Description
m_mdc
O
AF9
MII management data clock.
Common for both MII ports.
m_mdio
IOU
AC10
MII management data I/O
Common for both MII ports; 2.5 MHz
MII Port A
m_mint0
I U
AF6
MII management interrupt for port A
m0_txd[3:0]
O U
AC8 [3], AF5 [2], AE6 [1], AD7 [0]
Transmit data
m0_txen
O U
AD6
Transmit enable
Table 6 - MII Interfaces
Signal
I/O
Package Balls
Description
Table 5 - Local TDM Interface (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
| MT91600AN1 | Programmable SLIC |
| MT91600ANR | Programmable SLIC |
| MT91600ANR1 | Programmable SLIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。