參數(shù)資料
型號(hào): MT90870
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 12 k Digital Switch (F12kDX)
中文描述: 靈活的12畝數(shù)字交換機(jī)(F12kDX)
文件頁數(shù): 84/86頁
文件大?。?/td> 2093K
代理商: MT90870
MT90870
Data Sheet
84
Zarlink Semiconductor Inc.
Note:
1. High impedance is measured by pulling to the appropriate rail with R
L
= 1K/1K potential divider, with timing corrected to cancel time
taken to charge C
L
.
Figure 30 - Motorola Non-Multiplexed Bus Timing
Note: There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion
of CS and/or DS (to initiate the next access).
6
Address hold after DS rising
t
ADH
8
ns
7
Data setup from DTA Low on Read
t
DDR
t
DHR
14
ns
C
L
=60pF
8
Data hold on read
30
ns
C
L
=60pF, R
L
=1K
Note 1
9
Data setup on write
t
WDS
8
ns
10
Data hold on write
t
DHW
8
ns
11
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
t
AKD
85
70
ns
ns
C
L
=60pF
C
L
=60pF
12
Acknowledgment Hold Time
t
AKH
12
ns
C
L
=60pF, R
L
=1K,
Note 1
Non-Multiplexed Microprocessor Port Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
A0-A14
D0-D15
READ
D0-D15
WRITE
t
CSS
t
CSH
t
ADH
t
DHR
t
RWS
t
ADS
t
RWH
t
DHW
t
AKD
t
WDS
t
DDR
t
AKH
V
TT
V
TT
V
TT
V
TT
V
TT
V
TT
V
TT
VALID ADDRESS
VALID READ DATA
VALID WRITE DATA
DTA
R/W
CS
DS
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