- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359235 > MT90870 (Zarlink Semiconductor Inc.) Flexible 12 k Digital Switch (F12kDX) PDF資料下載
參數(shù)資料
| 型號： | MT90870 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 12 k Digital Switch (F12kDX) |
| 中文描述： | 靈活的12畝數(shù)字交換機（F12kDX） |
| 文件頁數(shù)： | 43/86頁 |
| 文件大小： | 2093K |
| 代理商： | MT90870 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
MT90870
Data Sheet
43
Zarlink Semiconductor Inc.
The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0, Microprocessor Port, and
Section 13.1, Control Register (CR) for details on microprocessor port access.
6.3 Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power
up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register
(BPR) will be loaded into the connection memories. See Table 16 and Table 17 for details of the Control Register
and Block Programming Register values, respectively.
6.3.1 Memory Block Programming Procedure
Set the
MBP
bit in the Control Register from LOW to HIGH.
Set the
BPE
bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0
, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively. of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 6.
Table 6 - Local Connection Memory in Block Programming Mode
The Backplane Block Programming data bits,
BBPD2-0
, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are loaded
with zeros as shown in Table 7.
Table 7 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125 us, to indicate completion of
memory programming. The Block Programming Mode can be terminated at any time prior to completion by setting
the
BPE
bit of the Block Programming Register or the MBP bit of the Control Register to LOW.
Note the default values (LOW) of
LBPD2-0
and
BBPD2-0
of the Block Programming Register, following a device
reset, may be used. These settings shall set all output channels to High, or High-Impedance, in accordance with the
LORS
and
BORS
pin conditions, see Pin Description for further details. The Local Connection Memory shall be
configured to select data from Channel 0 of Backplane input Stream 0 (
BSTi0
), and the Backplane Connection
Memory shall be configured to select data from Channel 0 of Local input Stream 0 (
LSTi0
). Alternative conditions
may be established by programming bits
LBPD2-0
and
BBPD2-0
of the Block Programming Register at the time of
setting Bit
BPE
to HIGH. See Section 12.3, Local Connection Memory Bit Definition, Section 12.4, Backplane
Connection Memory Bit Definition, and Section 13.2, Block Programming Register (BPR).
7.0 Microprocessor Port
The MT90870 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit
parallel data bus (
D0-15
), 15-bit address bus (
A0-14
) and four control signals (
CS, DS, R/W
and
DTA
). The data
bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local
Connection and Data memories. Each Backplane memory has 8,192 locations and each Local memory has 4,096
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD2
LBPD1
LBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBPD2
BBPD1
BBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90871AV | Flexible 8K Digital Switch (F8KDX) |
| MT90871 | Flexible 8K Digital Switch (F8KDX) |
| MT90883 | TDM to Packet Processors |
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90870AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90870AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90871 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX) |
| MT90871AV | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。