參數(shù)資料
型號: MT90870
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 12 k Digital Switch (F12kDX)
中文描述: 靈活的12畝數(shù)字交換機(jī)(F12kDX)
文件頁數(shù): 62/86頁
文件大?。?/td> 2093K
代理商: MT90870
MT90870
Data Sheet
62
Zarlink Semiconductor Inc.
The
LOAR0 to LOAR15
registers are configured as follows:
13.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Local frame pulse.
13.9 Backplane Output Advancement Registers (BOAR0 - 31)
Address 00A3h to 00C2h
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. For 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s stream operation
the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072MHz). For 32 Mb/ s stream
operation the possible adjustment is -1, -2 or -3 cycles of the internal system clock (131.072 MHz). The
BOAR0
to
BOAR3
registers are configured as follows:
13.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Backplane frame pulse.
LOARn Bit
(where n = 0 to 15)
Name
Reset
Description
15-2
Reserved
0
Reserved
1-0
LOA(1:0)
0
Local Output Advancement Register
Table 27 - Local Output Advancement Register (LOARn) Bits
Local Output Advancement
Corresponding Advancement Bits
Clock Rate 131.072 MHz
LOA1
LOA0
0 (Default)
0
0
-2 cycle
0
1
-4 cycles
1
0
-6 cycles
1
1
Table 28 - Local Output Advancement (LOAR) Programming Table
BOARn Bit
(where n = 0 to 31 for non-32 Mb/s
mode, n = 0 to 15 for 32 Mb/s mode)
Name
Reset
Description
15-2
Reserved
0
Reserved
1:0
BOA(1:0)
0
Backplane Output Advancement Register
Table 29 - Backplane Output Advancement Register (BOAR) Bits
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