參數(shù)資料
型號(hào)： MT90870
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 12 k Digital Switch (F12kDX)
中文描述： 靈活的12畝數(shù)字交換機(jī)（F12kDX）
文件頁(yè)數(shù)： 69/86頁(yè)
文件大?。?/td> 2093K
代理商： MT90870
MT90870
Data Sheet
69
Zarlink Semiconductor Inc.
13.14 Memory BIST Register
Address 014Dh
The Memory BIST register enables the built-in-self-test function for the on-chip memory testing. Two consecutive
write operations are required to start MBIST. The first with only Bit 12 (LV_TM) set High (i.e. 1000h), the second
with Bit 12 maintained High but with the required start bit(s) set High.
The
MBISTR
register is configured as follows:
BOBR1
BOBR0
Bit rate for stream n
0
0
2Mb/s
0
1
4Mb/s
1
0
8Mb/s
1
1
16Mb/s
Table 48 - Backplane Output Bit Rate (BOBRR) Programming Table
Bit
Name
Reset
Description
15-13
Reserved
0
Reserved.
12
LV_TM
0
MBIST Test enable.
High for MBIST mode, Low for scan mode.
11
BISTSDB
0
Backplane Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
10
BISTCDB
0
Backplane Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
9
BISTPDB
0
Backplane Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
8
BISTSDL
0
Local Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
7
BISTCDL
0
Local Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
6
BISTPDL
0
Local Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
5
BISTSCB
0
Backplane Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
4
BISTCCB
0
Backplane Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Table 49 - Memory BIST Register (MBISTR) Bits
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