參數(shù)資料
型號(hào)： MT90870
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 12 k Digital Switch (F12kDX)
中文描述： 靈活的12畝數(shù)字交換機(jī)（F12kDX）
文件頁數(shù)： 58/86頁
文件大?。?/td> 2093K
代理商： MT90870
MT90870
Data Sheet
58
Zarlink Semiconductor Inc.
13.5 Local Input Bit Delay Registers (LIDR0 to LIDR15)
Address 0023h to 0032h.
Sixteen Local input delay registers (LIDR0 to LIDR15) allow users to program the input bit delay for the Local input
data streams LSTi0-15. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a resolution
of 1/4 of the data rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s or 16 Mb/s.
The
LIDR0 to LIDR15
registers are configured as follows:
13.5.1 Local Input Delay Bits 4-0 (LID4 - LID0)
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit delay
adjustment can range up to 7
3
/
4
bit periods forward, with resolution of
1
/
4
bit period.
This can be described as: LIDn(4:0) = (no. of bits delay) / 4
For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 *
1
/
4
= 4
3
/
4.
Table 22, Local Input Bit Delay Programming Table, illustrates the bit delay selection.
LIDRn Bit
(where n = 0
to 15)
Name
Reset
Description
15-5
Reserved
0
Reserved
4-0
LIDn(4:0)
0
Local Input Bit Delay Register
The binary value of these bits refers to the input bit delay value
for the Local input stream
Table 21 - Local Channel Delay Register (LIDRn) Bits
Corresponding Delay Bits
Data Rate
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
LID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 22 - Local Input Bit Delay Programming Table
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