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參數(shù)資料
| 型號： | MT90870 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 12 k Digital Switch (F12kDX) |
| 中文描述： | 靈活的12畝數(shù)字交換機(jī)（F12kDX） |
| 文件頁數(shù)： | 44/86頁 |
| 文件大?。?/td> | 2093K |
| 代理商： | MT90870 |
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MT90870
Data Sheet
44
Zarlink Semiconductor Inc.
locations. See Table 8, Address Map for Data and Connection Memory Locations (A14=1), for the address
mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’ in the event of the MT90870 not receiving a master clock, the microprocessor port
shall complete the DTA handshake when accessed but any data read from the bus will be invalid.
There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e. a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of
CS and/or DS to initiate the next access).
8.0 Device Power-up, Initialization and Reset
8.1 Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3 V) to be established before the
power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8 V). The VDD_PLL and VDD_CORE supplies
may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
8.2 Initialization
Upon power up, the MT90870 should be initialized by applying the following sequence:
8.3 Reset
The
RESET
pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90870. It
is synchronized to the internal clock and remains active for 50 us following release (set HIGH) of the external
RESET
to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins
LORS
and
BORS
, the output streams
LSTo0-15
and
BSTo0-31
are set to high or high impedance, and all internal
registers and counters are reset to the default state.
The
RESET
pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release.
1
Ensure the
TRST
pin is permanently LOW to disable the JTAG TAP controller.
2
Set
ODE
pin to LOW. This configures the
LCSTo0-1
output signals to LOW (i.e., to set
optional external output buffers to high impedance), and sets the
LSTo0-15
outputs to high
or high impedance, dependent on the
LORS
input value, and sets the
BCSTo0-3
output
signals
to
LOW (i.e., to set optional external output buffers to high impedance), and sets the
BSTo0-31
outputs to high or high impedance, dependent on
BORS
input value. Refer to
Pin Description for details of the
LORS
and
BORS
pins.
3
Reset the device by pulsing the
RESET
pin to zero for at least two cycles of the input
clock,
C8i
.
4
Use the Block Programming Mode to initialize the Local and the Backplane Connection
Memories. Refer to Section 6.3, Connection Memory Block Programming.
5
Set
ODE
pin to HIGH after the connection memories are programmed to ensure that bus
contention will not occur at the serial stream outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT90870AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90870AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90871 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX) |
| MT90871AV | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
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