參數(shù)資料
型號(hào): MT90870
廠(chǎng)商: Zarlink Semiconductor Inc.
英文描述: Flexible 12 k Digital Switch (F12kDX)
中文描述: 靈活的12畝數(shù)字交換機(jī)(F12kDX)
文件頁(yè)數(shù): 59/86頁(yè)
文件大小: 2093K
代理商: MT90870
MT90870
Data Sheet
59
Zarlink Semiconductor Inc.
13.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR31)
Address 0043h to 0062h
Thirty-two Backplane input channel delay registers (BCDR0 to BCDR31) allow users to program the input channel
delay for the Backplane input data streams BSTi0-31. The possible adjustment is 511 channels and the
BCDR0 to
BCDR31
registers are configured as follows:
13.6.1 Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0)
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane stream input pins. The input channel delay can be set to 511 (32 Mb/s streams), 255 (16 Mb/s
streams), 127 (8 Mb/s streams), 63 (4 Mb/s streams) or 31 (2 Mb/s streams) from the frame boundary.
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
BCDRn Bit
(where n = 0 to 31 for non-32Mb/s
mode, n = 0 to 15 for 32Mb/s
mode)
Name
Reset
Description
15-9
Reserved
0
Reserved
8-0
BCD(8:0)
0
Backplane Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Backplane input stream
Table 23 - Backplane Channel Delay Register (BCDRn) Bits
Corresponding Delay Bits
Data Rate
LID4
LID3
LID2
LID1
LID0
Table 22 - Local Input Bit Delay Programming Table (continued)
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