參數資料
型號: MT90870
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 12 k Digital Switch (F12kDX)
中文描述: 靈活的12畝數字交換機(F12kDX)
文件頁數: 63/86頁
文件大?。?/td> 2093K
代理商: MT90870
MT90870
Data Sheet
63
Zarlink Semiconductor Inc.
13.10 Local Bit Error Rate (BER) Registers
13.10.1 Local BER Start Send Register (LBSSR)
Address 00C3h.
Local BER Start Send Register defines the output channel and the stream in which the BER sequence starts to
be transmitted. The
LBSSR
register is configured as follows:
13.10.2 Local Transmit BER Length Register (LTXBLR)
Address 00C4h
Local BER Transmit Length Register (
LTXBLR
) defines how many channels the BER sequence will be transmitted
during each frame. The
LTXBLR
register is configured as follows:
Backplane Output Advancement For
2 Mb/s, 4 Mb/s, 8 Mb/s & 16 Mb/s
Backplane Output
Advancement For 32 Mb/s
Corresponding
Advancement Bits
clock Rate 131.072 MHz
clock Rate 131.072 MHz
BOA1
BOA0
0 (Default)
0 (Default)
0
0
-2 cycle
-1 cycle
0
1
-4 cycles
-2 cycle
1
0
-6 cycles
-3 cycle
1
1
Table 30 - Backplane Output Advancement (BOAR) Programming Table
Bit
Name
Reset
Description
15-12
Reserved
0
Reserved.
11-8
LBSSA(3:0)
0
Local BER Send Stream Address Bits.
The binary value of these bits refers to the Local output stream
which carries the BER data.
7-0
LBSCA(7:0)
0
Local BER Send Channel Address Bits.
The binary value of these bits refers to the Local output channel in
which the BER data starts to be sent.
Table 31 - Local BER Start Send Register (LBSSR) Bits
Bit
Name
Reset
Description
15-8
Reserved
0
Reserved
.
Table 32 - Local Transmit BER Length Register (LTXBLR) Bits
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