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參數(shù)資料
| 型號： | MT90870 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 12 k Digital Switch (F12kDX) |
| 中文描述： | 靈活的12畝數(shù)字交換機（F12kDX） |
| 文件頁數(shù)： | 29/86頁 |
| 文件大?。?/td> | 2093K |
| 代理商： | MT90870 |
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MT90870
Data Sheet
29
Zarlink Semiconductor Inc.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0,
LSTo0_Ch0,
is transmitted on
LCSTo0
and is
advanced, relative to the Frame Boundary, by 10 periods of
C16o
.
(2) The Channel Control Bit corresponding to Stream 14, Channel 0,
LSTo14_Ch0,
is transmitted on
LCSTo0
in
advance of the Frame Boundary by three periods of output clock,
C16o
. Similarly, the Channel Control Bit for
LSTo15_Ch0
, is advanced relative to the Frame Boundary by three periods of
C16o
, on
LCSTo1
.
The
LCSTo0-1
outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for the
individual output streams,
LSTo0-15
. Streams at data-rates lower than 16.384 Mb/s will have the value of the
respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192 Mb/s
streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel control bit is not
repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 2:
(3) With stream
LSTo4
selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel Control
Bit for
Channel 0
will be transmitted during the
C16o
clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and
48.
(4) With stream
LSTo8
operated at a data-rate of 8.192 Mb/s, the value of the Channel Control Bit for
Channel 1
will be transmitted during the
C16o
clock period nos. 9 and 17.
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus Mode) shows the channel control bits for
LCSTo0
and
LCSTo1
in one possible scenario which includes stream
LSTo0
at a data-rate of 16.384 Mb/s,
LSTo1
at 8.192 Mb/s,
LSTo6
at 4.096 Mb/s and
LSTo7
at 2.048 Mb/s. All remaining streams are operated at a data-rate of
16.384 Mb/s.
4.1.2
LORS Set HIGH
The Local Output Enable Bit (
LE
) of the Local Connection Memory has direct per-channel control on the high-
impedance state of the Local Output streams,
LSTo0-15
. Programming the
LE
bit to a LOW state will set the
stream output of the MT90870 to High Impedance for the duration of the channel period. See Section 12.3, Local
Connection Memory Bit Definition, for programming details.
The
LCSTo0-1
outputs remain active.
Allocated Stream No.
Allocated Channel No.
2
C16o
Period
1
LCSTo0
LCSTo1
16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
2039
0
3-1
2
3-3
1
Ch 0
Ch 0
Ch 0
Ch 0
2040
3
Ch 0
Ch 0
Ch 0
Ch 0
2041
4
5
Ch 0
Ch 0
Ch 0
Ch 0
2042
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2043
8
9
Ch 0
Ch 0
Ch 0
Ch 0
2044
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2045
12
14
3-2
13
15
3-2
Ch 0
Ch 0
Ch 0
Ch 0
2046
Ch 0
Ch 0
Ch 0
Ch 0
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90870AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90870AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90871 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX) |
| MT90871AV | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
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