參數(shù)資料
型號： MT90870
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 12 k Digital Switch (F12kDX)
中文描述： 靈活的12畝數(shù)字交換機(jī)（F12kDX）
文件頁數(shù)： 60/86頁
文件大?。?/td> 2093K
代理商： MT90870
MT90870
Data Sheet
60
Zarlink Semiconductor Inc.
13.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Address 0063h to 0082h
Thirty-two Backplane input delay registers (BIDR0 to BIDR31) allow users to program the input bit delay for the
Backplane input data streams BSTi0-31. The possible adjustment is 7 3/4 of the data rate, in steps of 1/4 of the
data rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s, 16 Mb/s, or 32 Mb/s.
The
BIDR0 to BIDR31
registers are configured as follows:
13.7.1 Backplane Input Delay Bits 4-0 (BID4 - BID0)
These five bits define how long in the cycle the serial interface receiver takes to recognize and stores the bit 0 from
the BSTi input pins: i.e., start assuming a new frame. Input bit delay adjustment can range up to 7
3
/
4
bit periods
forward with resolution of
1
/
4
bit period.
This can be described as BIDn(4:0) = (no. of bits delay) / 4
For example, if BID(4:0) is set to 10011 (19), the input bit delay = 19 *
1
/
4
= 4
3
/
4.
Input Stream
Channel Delay
Corresponding Delay Bits
BCD8-BCD0
0 Channel (Default)
0 0000 0000
1 Channel
0 0000 0001
2 Channels
0 0000 0010
3 Channels
0 0000 0011
4 Channels
0 0000 0100
5 Channels
0 0000 0101
...
...
...
...
509 Channels
1 1111 1101
510 Channels
1 1111 1110
511 Channels
1 1111 1111
Table 24 - Backplane Input Channel Delay (BCD) Programming Table
BIDRn Bit
(where n = 0 to 31 for Non-32Mb/s
Mode, n = 0 to15 for 32Mb/s Mode)
Name
Reset
Description
15-5
Reserved
0
Reserved
4-0
BID(4:0)
0
Backplane Input Bit Delay Register
The binary value of these bits refers to the input bit
delay value for the Backplane input stream
Table 25 - Backplane Input Bit Delay Register (BIDRn) Bits
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