參數(shù)資料
型號(hào)： MT48LC8M8A2TG-8EL:GIT
元件分類(lèi)： DRAM
英文描述： 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 7/55頁(yè)
文件大?。?/td> 1454K
15
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last ele-
ment of a completed burst or the last desired data ele-
ment of a longer burst which is being truncated.
The new READ command should be issued x cycles
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A9: x4
A0-A8: x8
A0-A7: x16
A10
BA0,1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A11: x4
A9, A11: x8
A8, A9, A11: x16
相關(guān)PDF資料
PDF描述
MT4JSF6464HIY-80BXX 64M X 64 DDR DRAM MODULE, ZMA204
MT4JSF6464HY-1G4XX 64M X 64 DDR DRAM MODULE, ZMA204
MT4LC16M4A7DJ-6S 16M X 4 FAST PAGE DRAM, 60 ns, PDSO32
MT58L128L36P1T-5 128K X 36 CACHE SRAM, 2.8 ns, PQFP100
MT58L512Y36FT-8.5 512K X 36 CACHE SRAM, 8.5 ns, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LCM32B2P 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SDR SDRAM MT48LC2M32B2 a?? 512K x 32 x 4 Banks
MT48NN 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類(lèi)型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類(lèi)型: 位置/觸點(diǎn)數(shù)量:48
MT48NNX 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類(lèi)型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類(lèi)型: 位置/觸點(diǎn)數(shù)量:48
MT48NS 功能描述:插線板 1 RU PANEL 48 LF JA RoHS:否 制造商:Switchcraft 產(chǎn)品類(lèi)型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類(lèi)型: 位置/觸點(diǎn)數(shù)量:48
MT48NSX 功能描述:插線板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 產(chǎn)品類(lèi)型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類(lèi)型: 位置/觸點(diǎn)數(shù)量:48
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*