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參數(shù)資料
| 型號： | MT48LC8M8A2TG-8EL:GIT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 6/55頁 |
| 文件大?。?/td> | 1454K |
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14
64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a tRCD specifi-
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
which covers any case where 2 < tRCD (MIN)/tCK
≤ 3.
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
Figure 4
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
CLK
T2
T1
T3
T0
t
COMMAND
NOP
ACTIVE
READ or
WRITE
T4
NOP
RCD
DON’T CARE
CS#
WE#
CAS#
RAS#
CKE
CLK
A0–A10, A11
ROW
ADDRESS
HIGH
BA0, BA1
BANK
ADDRESS
Figure 3
Activating a Specific Row in a
Specific Bank
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LCM32B2P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SDR SDRAM MT48LC2M32B2 a?? 512K x 32 x 4 Banks |
| MT48NN | 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| MT48NNX | 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| MT48NS | 功能描述:插線板 1 RU PANEL 48 LF JA RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
| MT48NSX | 功能描述:插線板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
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