
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM
2003 Micron Technology, Inc.
MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03
1
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH SYNCBURST SRAM
18Mb SYNCBURST
SRAM
MT58L1MY18F, MT58V1MV18F,
MT58L512Y32F, MT58V512V32F,
MT58L512Y36F, MT58V512V36F
3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O
Features
Fast clock and OE# access times
Single 3.3V ±5 percent or 2.5V ±5 percent power supply
Separate 3.3V±5 percent or 2.5V ±5 percent isolated
output buffer supply (VDDQ)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual byte write control and global write
Three chip enables for simple depth expansion and
address pipelining
Clock-controlled and registered addresses, data
I/Os, and control signals
Internally self-timed write cycle
Burst control (interleaved or linear burst)
Low capacitive bus loading
Part Number Example:
MT58L512Y36FT-10
General Description
The Micron SyncBurst SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
(CE#), two additional chip enables for easy depth
expansion (CE2#, CE2), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#), and global
write (GW#).
Options
TQFP
Marking
Timing (Access/Cycle/MHz)
6.8ns/7.5ns/133 MHz
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
-6.8
-7.5
-8.5
-10
Configurations
3.3V VDD, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
MT58L1MY18F
MT58L512Y32F
MT58L512Y36F
2.5V VDD, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
MT58V1MV18F
MT58V512V32F
MT58V512V36F
Packages
100-pin TQFP
165-ball, 13mm x 15mm FBGA
T
F1
NOTE:
1. A Part Marking Guide for the FBGA devices can be found on
Operating Temperature Range
Commercial (0C
TA +70C)
None
Industrial (-40C
TA +85C)
IT2
2. Contact factory for availability of Industrial Temperature
devices.
Figure 1: 100-Pin TQFP
JEDEC-Standard MS-026 BHA (LQFP)
Figure 2: 165-Ball FBGA
JEDEC-Standard MO-216 (Var. CAB-1)