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參數(shù)資料
| 型號(hào)： | MT58L512Y36FT-8.5 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 CACHE SRAM, 8.5 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大小： | 537K |
| 代理商： | MT58L512Y36FT-8.5 |
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18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03
2
2003 Micron Technology, Inc.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data out (Q) is
enabled by OE#. WRITE cycles can be from one to two
bytes wide (x18) or from one to four bytes wide (x32/
x36), as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst
advance input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed write
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins/balls and DQPa; BWb# con-
trols DQb pins/balls and DQPb. During WRITE cycles
on the x32 and x36 devices, BWa# controls DQa pins/
balls and DQPa; BWb# controls DQb pins/balls and
DQPb; BWc# controls DQc pins/balls and DQPc; BWd#
controls DQd pins/balls and DQPd. GW# LOW causes
all bytes to be written. Parity bits are only available on
the x18 and x36 versions.
The device is ideally suited for 486, Pentium, 680x0
and PowerPC systems and those systems that benefit
from a wide synchronous data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
Dual Voltage I/O
The 3.3V VDD device is tested for 3.3V and 2.5V I/O
function. The 2.5V VDD device is tested for only 2.5V
I/O function.
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PDF描述 |
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| MT58V1MV18DT-10 | 1M X 18 CACHE SRAM, 5 ns, PQFP100 |
| MT5C2565EC-70/IT | 64K X 4 STANDARD SRAM, 70 ns, CQCC28 |
| MT5C256K16B2DJ-12PAT | 256K X 16 STANDARD SRAM, 12 ns, PDSO54 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512Y36PF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y36PF-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y36PT10 | 制造商:MT 功能描述:New |
| MT58L512Y36PT-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512Y36PT-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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