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參數(shù)資料
| 型號： | MT58L512Y36FT-8.5 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 CACHE SRAM, 8.5 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 10/34頁 |
| 文件大?。?/td> | 537K |
| 代理商： | MT58L512Y36FT-8.5 |
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18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03
18
2003 Micron Technology, Inc.
Figure 7:
READ Timing
NOTE:
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following
A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. (This note applies to
whole diagram.)
4. Outputs are disabled tKQHZ after deselect.
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST
READ
tOEQ
tOELZ
tKQHZ
Burst wraps around
to its initial state
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
A2
(NOTE 1)
ADV# suspends burst.
Deselect Cycle
(Note 4)
BWE#, GW#,
BWa#-BWd#
DON’T CARE
UNDEFINED
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PDF描述 |
|---|---|
| MT58V1MV18DT-10 | 1M X 18 CACHE SRAM, 5 ns, PQFP100 |
| MT5C2565EC-70/IT | 64K X 4 STANDARD SRAM, 70 ns, CQCC28 |
| MT5C256K16B2DJ-12PAT | 256K X 16 STANDARD SRAM, 12 ns, PDSO54 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512Y36PF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y36PF-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y36PT10 | 制造商:MT 功能描述:New |
| MT58L512Y36PT-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58L512Y36PT-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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