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參數(shù)資料
| 型號： | MT48LC8M8A2TG-8EL:GIT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 25/55頁 |
| 文件大?。?/td> | 1454K |
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64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
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| MT48LCM32B2P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SDR SDRAM MT48LC2M32B2 a?? 512K x 32 x 4 Banks |
| MT48NN | 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類型: 位置/觸點(diǎn)數(shù)量:48 |
| MT48NNX | 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類型: 位置/觸點(diǎn)數(shù)量:48 |
| MT48NS | 功能描述:插線板 1 RU PANEL 48 LF JA RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類型: 位置/觸點(diǎn)數(shù)量:48 |
| MT48NSX | 功能描述:插線板 1/4" LF SLDR BAY 1RU, 2X24, NORM STR RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類型: 位置/觸點(diǎn)數(shù)量:48 |
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