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參數(shù)資料
| 型號： | MT48LC8M8A2TG-8EL:GIT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 21/55頁 |
| 文件大?。?/td> | 1454K |
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64Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM.pmd – Rev. H; Pub. 12/04
2002 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16
SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS#CAS# WE#
COMMAND (ACTION)
NOTES
Any
H
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
NO OPERATION (NOP/Continue previous operation)
L
H
ACTIVE (Select and activate row)
Idle
L
H
AUTO REFRESH
7
L
LOAD MODE REGISTER
7
L
H
L
PRECHARGE
11
L
H
L
H
READ (Select column and start READ burst)
10
Row Active
L
H
L
WRITE (Select column and start WRITE burst)
10
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
Read
L
H
L
H
READ (Select column and start new READ burst)
10
(Auto
L
H
L
WRITE (Select column and start WRITE burst)
10
Precharge
L
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
8
Disabled)
L
H
L
BURST TERMINATE
9
Write
L
H
L
H
READ (Select column and start READ burst)
10
(Auto
L
H
L
WRITE (Select column and start new WRITE burst)
10
Precharge
L
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
8
Disabled)
L
H
L
BURST TERMINATE
9
NOTE:
1. This table applies when CKE
n-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet termi-
nated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is
met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is
met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
tRP has been met. Once tRP is met, the bank will be in the idle state.
(Continued on next page)
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| MT48NN | 功能描述:插線板 48POS AUDIO PATCHBAY RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機架數(shù)量: 深度: 端接類型: 位置/觸點數(shù)量:48 |
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